ROHS MC9S08QE128 Reference Manual

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MC9S08QE128

MC9S08QE96

MC9S08QE64

Reference Manual

HCS08

Microcontrollers

MC9S08QE128RM

Rev. 2

6/2007

freescale.com

Summary of Contents for ROHS MC9S08QE128

Page 1 MC9S08QE128 MC9S08QE96 MC9S08QE64 Reference Manual Related Documentation: HCS08 Microcontrollers • MC9S08QE128 (Data Sheet) Contains pin assignments and diagrams, all electrical speciﬁcations, and mechanical drawing outlines. Find the most current versions of all documents at: http://www.freescale.com MC9S08QE128RM Rev. 2 6/2007 freescale.com...
Page 3 MC9S08QE128 Series Features 8-Bit HCS08 Central Processor Unit (CPU) Development Support • Up to 50.33-MHz HCS08 CPU from 3.6 V to 2.1 V, and • Single-wire background debug interface 20-MHz CPU at 2.1 V to 1.8 V across temperature range •...
Page 5: Freescale Semiconductor
MC9S08QE128 Reference Manual Covers MC9S08QE128 MC9S08QE96 MC9S08QE64 MC9S08QE128RM Rev. 2 6/2007 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007. All rights reserved. Get the latest version from freescale.com...
Page 6: Freescale Semiconductor
Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document.
Page 7 Serial Communications Interface (S08SCIV4)......247 Chapter 15 Serial Peripheral Interface (S08SPIV3) ........267 Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) ......... 283 Chapter 17 Development Support ..............307 Chapter 18 Debug Module (DBG) (128K)............321 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 8: Table Of Contents
3.6.5 Stop modes in Low Power Run Mode ................45 Mode Selection ..........................45 3.7.1 On-Chip Peripheral Modules in Stop and Low Power Modes ..........48 Chapter 4 Memory MC9S08QE128 Series Memory Map .....................51 Reset and Interrupt Vector Assignments ..................53 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 9: Section Number Title Page
5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ......105 5.8.9 System Power Management Status and Control 3 Register (SPMSC3) ......106 5.8.10 System Clock Gating Control 1 Register (SCGC1) ............107 5.8.11 System Clock Gating Control 2 Register (SCGC2) ............108 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 10 7.3.3 KBI Interrupt Edge Select Register (KBIxES) ...............142 Functional Description ........................142 7.4.1 Edge Only Sensitivity .....................143 7.4.2 Edge and Level Sensitivity ....................143 7.4.3 Pull-Up/Pull-Down Resistors ..................143 7.4.4 Keyboard Interrupt Initialization ..................143 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 11 9.1.4 Interrupt Vectors ......................168 9.1.5 Features ...........................170 9.1.6 Modes of Operation ......................170 9.1.7 Block Diagram ........................170 External Signal Description ......................171 Register Deﬁnition ........................171 9.3.1 ACMPx Status and Control Register (ACMPxSC) ............172 Functional Description ........................173 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 12 10.4.8 MCU Stop1 and Stop2 Mode Operation .................195 10.5 Initialization Information ......................195 10.5.1 ADC Module Initialization Example ................195 10.6 Application Information ........................197 10.6.1 External Pins and Routing ....................197 10.6.2 Sources of Error ......................199 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 13 12.3.1 IIC Address Register (IICxA) ..................221 12.3.2 IIC Frequency Divider Register (IICxF) .................222 12.3.3 IIC Control Register (IICxC1) ..................224 12.3.4 IIC Status Register (IICxS) .....................225 12.3.5 IIC Data I/O Register (IICxD) ..................226 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 14 14.1.1 SCI Clock Gating ......................247 14.1.2 Interrupt Vectors ......................247 14.1.3 Features ...........................250 14.1.4 Modes of Operation ......................250 14.1.5 Block Diagram ........................251 14.2 Register Deﬁnition ........................253 14.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ............253 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 15 15.4.5 SPI Data Register (SPIxD) ....................277 15.5 Functional Description ........................278 15.5.1 SPI Clock Formats ......................278 15.5.2 SPI Interrupts ........................281 15.5.3 Mode Fault Detection .....................281 Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) 16.1 Introduction ...........................283 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 16 17.2.2 Communication Details ....................309 17.2.3 BDC Commands ......................313 17.2.4 BDC Hardware Breakpoint .....................315 17.3 Register Deﬁnition ........................315 17.3.1 BDC Registers and Control Bits ..................316 17.3.2 System Background Debug Force Reset Register (SBDFR) ..........318 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 17 18.4.1 Comparator ........................338 18.4.2 Breakpoints ........................339 18.4.3 Trigger Selection ......................339 18.4.4 Trigger Break Control (TBC) ..................340 18.4.5 FIFO ..........................343 18.4.6 Interrupt Priority ......................344 18.5 Resets ............................344 18.6 Interrupts ............................345 18.7 Electrical Speciﬁcations ........................345 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 18: Devices In The Mc9S08Qe128 Series
Chapter 1 Device Overview The MC9S08QE128, MC9S08QE96, and MC9S08QE64 are members of the low-cost, low-power, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types.
Page 19: Device Overview
Chapter 1 Device Overview MCU Block Diagram The block diagram in Figure 1-1 shows the structure of the MC9S08QE128 Series MCU. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 20: Mcu Block Diagram
V in 48-pin and 32-pin packages PTG1 REFH REFL PTH0 and V pins are each internally connected to two pads in 32-pin package PTG0 Figure 1-1. MC9S08QE128 Series Block Diagram MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 21: Freescale Semiconductor
(ICS) Keyboard Interrupt (KBI) Low Power Oscillator (XOSCVLP) On-Chip In-Circuit Debug/Emulator (DBG) Port Set/Clear (PSC) Real-Time Counter (RTC) Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) Timer Pulse Width Modulator (TPM) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 22: Freescale Semiconductor
TPMxCLK — TPMxCLKs are optional external clock sources for the TPM modules. The TPMxCLK must be limited to 1/4th the frequency of the bus clock for synchronization. See the External TPM Clock Sources section in Chapter 16, “Timer/Pulse-Width Modulator (S08TPMV3) for more details. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 23: System Clock Distribution
EXTAL XTAL of the bus clock frequency. See the ADC chapter and erase operation. See and data sheet for the data sheet for details. details. Figure 1-2. System Clock Distribution Diagram MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 24: Pins And Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. Device Pin Assignment This section shows the pin assignments for MC9S08QE128 Series devices in the available packages. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 25: Pins And Connections
SSAD PTE4 PTA6/TPM1CH2/ADP8 PTB7/SCL1/EXTAL PTA7/TPM2CH2/ADP9 PTB6/SDA1/XTAL PTF2/ADP12 PTH3 PTF3/ADP13 PTH2 PTJ2 PTH1 PTJ3 PTH0 PTB0/KBI1P4/RxD1/ADP4 PTE6 PTB1/KBI1P5/TxD1/ADP5 Pins in bold are added from the next smaller package. Figure 2-1. 80-Pin LQFP MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 26: Freescale Semiconductor
PTF1/ADP11 DDAD REFH REFL PTE4 SSAD PTA6/TPM1CH2/ADP8 PTB7/SCL1/EXTAL PTA7/TPM2CH2/ADP9 PTB6/SDA1/XTAL PTF2/ADP12 PTF3/ADP13 PTH1 PTB0/KBI1P4/RxD1/ADP4 PTH0 PTB1/KBI1P5/TxD1/ADP5 PTE6 Pins in bold are added from the next smaller package. Figure 2-2. 64-Pin LQFP MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 27: Freescale Semiconductor
PTD0/KBI2P0/SPSCK2 PTD2/KBI2P2/MISO2 PTE7/TPM3CLK PTD3/KBI2P3/SS2 PTD4/KBI2P4 DDAD REFH REFL PTE4 SSAD PTA6/TPM1CH2/ADP8 PTB7/SCL1/EXTAL PTA7/TPM2CH2/ADP9 PTB6/SDA11/XTAL PTB0/KBI1P4/RxD1/ADP4 PTE6 PTB1/KBI1P5/TxD1/ADP5 Pins in bold are added from the next smaller package. Figure 2-3. 48-Pin QFN MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 28: Freescale Semiconductor
PTA2/KBI1P2/SDA1/ADP2 PTD0/KBI2P0/SPSCK2 PTA3/KBI1P3/SCL1/ADP3 PTD2/KBI2P2/MISO2 PTE7/TPM3CLK PTD3/KBI2P3/SS2 PTD4/KBI2P4 DDAD REFH REFL PTA6/TPM1CH2/ADP8 SSAD PTA7/TPM2CH2/ADP9 PTB0/KBI1P4/RxD1/ADP4 PTB7/SCL1/EXTAL PTB1/KBI1P5/TxD1/ADP5 PTB6/SDA1/XTAL Pins in bold are added from the next smaller package. Figure 2-4. 44-Pin QFP MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 29: Freescale Semiconductor
Chapter 2 Pins and Connections PTD1/KBI2P1/MOSI2 PTA2/KBIP2/SDA1/ADP2 PTD0/KBI2P0/SPSCK2 PTA3/KBIP3/SCL1/ADP3 PTD2/KBI2P2/MISO2 PTD3/KBI2P3/SS2 REFH DDAD PTA6/TPM1CH2/ADP8 REFL SSAD PTA7/TPM2CH2/ADP9 PTB0/KBI1P4/RxD1/ADP4 PTB7/SCL1/EXTAL PTB1/KBI1P5/TxD1/ADP5 PTB6/SDA1/XTAL Figure 2-5. 32-Pin LQFP MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 30: Freescale Semiconductor
Chapter 2 Pins and Connections Recommended System Connections Figure 2-6 shows pin connections that are common to MC9S08QE128 Series application systems. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 31: Recommended System Connections
PTG5/ADP21 PTH5 recommended for PTG6/ADP22 PTH6/SCL2 noisy environments. 4. C , and R PTG7/ADP23 PTH7/SDA2 are not required when low range low power oscillator is selected. Figure 2-6. Basic System Connections MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 32: Power
0.1-μF ceramic bypass capacitor located as near to the MCU power pins as practical to suppress high-frequency noise. Actual decoupling capacitor values and number will vary according to layout and application. The MC9S08QE128 Series has two V pins except on the 32-pin package.
Page 33: Reset And Rsto
BDC clock could be as fast as the bus clock rate, so there should never be any signiﬁcant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 34: General-Purpose I/O And Peripheral Ports
2.2.6 General-Purpose I/O and Peripheral Ports The MC9S08QE128 Series of MCUs support up to 70 general-purpose I/O pins 1 input-only pin, and 1 output-only pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, ACMP, etc.). When a port pin is conﬁgured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control.
Page 35: Adc Reference Pins
TPM3CH1 PTC0 TPM3CH0 — — — PTF7 ADP17 — — — PTF6 ADP16 — — — PTF5 ADP15 — — — PTF4 ADP14 PTB3 KBI1P7 MOSI1 ADP7 PTB2 KBI1P6 SPSCK1 ADP6 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 36 — — PTG2 ADP18 — — — PTG1 — — — PTG0 — PTE1 MOSI1 — PTE0 TPM2CLK SPSCK1 PTC5 TPM3CH5 ACMP2O PTC4 TPM3CH4 RSTO PTA5 TPM1CLK RESET PTA4 ACMP1O BKGD MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 37 SPI1 pins (SS1, MISO1, MOSI1, and SPSCK1) can be repositioned using SPI1PS in SOPT2. Default locations are PTB5, PTB4, PTB3, and PTB2. If ADC and ACMP1 are enabled, both modules will have access to the pin. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 38: Modes Of Operation 3.1 Introduction
— Stop2 — Partial power down of internal circuits, RAM content is retained; I/O states are held Run Mode This is the normal operating mode for the MC9S08QE128 Series. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset.
Page 39: Low Power Run Mode (Lprun)
If a device is in low power wait mode, a falling edge on an active BKGD/MS pin exits low power wait mode, clears the LPR and LPRS bits, and returns the device to normal run mode. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 40 The active background mode is used to program a bootloader or user application program into the ﬂash program memory before the MCU is operated in run mode for the ﬁrst time. When the MC9S08QE128 Series is shipped from the Freescale Semiconductor factory, the ﬂash program memory is erased by default unless speciﬁcally noted, so there is no program that could be executed in run mode until the ﬂash memory...
Page 41: Active Background Mode
In stop2 the regulator is in partial powerdown. The ICS module can be conﬁgured to leave the reference clocks running. See Chapter 11, “Internal Clock Source (S08ICSV3)” for more information. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 42: Low Power Wait Mode (Lpwait)
MCU is in stop2. The pullup on this pin is not automatically enabled in stop2. To enable the internal pullup, set the PTAPE5 bit in the port A pull enable register (PTAPE). MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 43 Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 44: Stop3 Mode
Mode Selection Several control signals are used to determine the current operating mode of the device. Table 3-2 shows the conditions for each of the device’s operating modes. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 45: Active Bdm Enabled In Stop Mode
Table 3-2. Power Mode Selections BDCSCR SPMSC1 SPMSC2 Effects on Sub-System Mode of Operation CPU & Periph CLKs Voltage ENBDM LVDE LVDSE PPDC BDM Clock Regulator RUN mode on. ICS in any mode. LPRUN mode low freq required. ICS in standby FBELP mode only.
Page 46 Standby STOP2 Partial power off WAIT LPWAIT Figure 3-1. Allowable Power Mode Transitions for the MC9S08QE128 Series Figure 3-1 illustrates mode state transitions allowed between the legal states shown in Table 3-1. PTA5/IRQ/TPM1CLK/RESET must be asserted low (or an RTC interrupt must occur) in order to exit stop2.
Page 47 Standby Optionally On Optionally On Wake Up Optionally On Optionally On Optionally On KBIx Optionally On Optionally On Optionally On LVD/LVW Optionally On Optionally On Optionally On Optionally On Optionally On MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 48: On-Chip Peripheral Modules In Stop And Low Power Modes
If LVDSE is set when entering LPRun or LPWait, the MCU will actually enter run or wait mode, respectively. Requires the LVD to be enabled, else in standby. See Section 3.6.4, “LVD Enabled in Stop Mode”. ERCLKEN and EREFSTEN set in ICSC2, else in standby. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 49 Chapter 3 Modes of Operation MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 50: Memory
4-1, Figure 4-2, and Figure 4-3, on-chip memory in the MC9S08QE128 Series of MCUs consists of RAM, ﬂash program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x007F) •...
Page 51: Mc9S08Qe128 Series Memory Map
4-1, Figure 4-2, and Figure 4-3, on-chip memory in the MC9S08QE128 Series of MCUs consists of RAM, ﬂash program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x007F) •...
Page 52 Paging Window - PPAGE=0 Extended addresses formed FLASH with PPAGE and 16384 BYTES A13:A0 of CPU address 0xBFFF 0x0BFFF 0xC000 0x0C000 PPAGE=3 FLASH 16384 BYTES 0xFFFF 0x0FFFF Figure 4-2. MC9S08QE96 Memory Map MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 53: Reset And Interrupt Vector Assignments
Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor provided equate file for the MC9S08QE128 Series. Table 4-1. Reset and Interrupt Vectors Address...
Page 54 KBI1 and KBI2 share this vector, if both modules are enabled user should poll each ﬂag to determine pending interrupt. IIC1 and IIC2 share this vector, if both modules are enabled user should poll each ﬂag to determine pending interrupt. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 55: Register Addresses And Bit Assignments
Chapter 4 Memory Register Addresses and Bit Assignments The registers in the MC9S08QE128 Series are divided into these groups: • Direct-page registers are located in the ﬁrst 128 locations in the memory map; these are accessible with efﬁcient direct addressing mode instructions.
Page 56 BRK13 LBKDE 0x0026 SCI1C3 TXDIR TXINV ORIE NEIE FEIE PEIE 0x0027 SCI1D Bit 7 Bit 0 0x0028 SPI1C1 SPIE SPTIE MSTR CPOL CPHA SSOE LSBFE 0x0029 SPI1C2 MODFEN BIDIROE SPISWAI SPC0 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 57 — — — — — — — 0x0050 TPM2SC TOIE CPWMS CLKSB CLKSA 0x0051 TPM2CNTH Bit 15 Bit 8 0x0052 TPM2CNTL Bit 7 Bit 0 0x0053 TPM2MODH Bit 15 Bit 8 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 58 ELS5A 0x0075 TPM3C5VH Bit 15 Bit 8 0x0076 TPM3C5VL Bit 7 Bit 0 0x0077 Reserved — — — — — — — — 0x0078 PPAGE XA16 XA15 XA14 0x0079 LAP2 LA16 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 59 Bit 16 0x1819 DBGCBX RWBEN PAGSEL Bit 16 0x181A DBGCCX RWCEN PAGSEL Bit 16 0x181B DBGFX PPACC Bit 16 0x181C DBGC DBGEN BRKEN LOOP1 0x181D DBGT TRGSEL BEGIN 0x181E DBGS ARMF MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 60 PTDSE0 0x184E PTDDS PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0 0x184F Reserved — — — — — — — — 0x1850 PTEPE PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 61 PTESET7 PTESET6 PTESET5 PTESET4 PTESET3 PTESET2 PTESET1 PTESET0 0x187A PTCCLR PTCCLR7 PTCCLR6 PTCCLR5 PTCCLR4 PTCCLR3 PTCCLR2 PTCCLR1 PTCCLR0 0x187B PTECLR PTECLR7 PTECLR6 PTECLR5 PTECLR4 PTECLR3 PTECLR2 PTECLR1 PTECLR0 0x187C PTCTOG PTCTOG7 PTCTOG6 PTCTOG5 PTCTOG4 PTCTOG3 PTCTOG2 PTCTOG1 PTCTOG0 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 62 1. IFR — Nonvolatile information memory that can be only accessed during production test. During production test, system initialization, conﬁguration and test information is stored in the IFR. This information cannot be read or modiﬁed in normal user or background debug modes. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 63: Memory Management Unit
— supports word accesses to any address speciﬁed by the linear address pointer when using LDHX, STHX instructions 4.4.2 Register Deﬁnition from 64 basic, to 128K in MC9S08QE128 4.4.2.1 Program Page Register (PPAGE) The HCS08 Core architecture limits the CPU addressable space available to 64K bytes. The address space can be extended to 128K bytes using a paging window scheme.
Page 64 When LWP is accessed the contents of LAP2:LAP0 make up the extended address of the ﬂash memory location to be addressed. When accessing data using LWP, the contents of LAP2:LAP0 will increment after the read or write is complete. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 65 LAP2:LAP0. Writes to this register will ﬁrst write the data value to the memory location speciﬁed by the linear address pointer and then will increment LAP2:LAP0. Writes to this register are most commonly used when writing to the ﬂash block(s) during programming. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 66: Functional Description
(PPAGE) allows for integrating up to 4M byte of ﬂash into the system by selecting one of the 16K byte blocks to be accessed through the paging window located at 0x8000-0xBFFF. The MMU module also provides a linear address pointer that allows extension of data access up to 4M bytes. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 67 Resumes execution at the return address This sequence is not interruptible; there is no need to inhibit interrupts during RTC execution. An RTC can be executed from any address in memory. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 68 MMU to add that value to the existing value in LAP2:LAP0. 4.4.3.1.4 PPAGE and Linear Address Pointer to Extended Address Figure 4-1, on how the program PPAGE memory pages and the Linear Address Pointer are mapped to extended address space. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 69: Ram
For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08QE128 Series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Page 70: Features
Features of the ﬂash memory include: • Flash size — MC9S08QE128: 131,072 bytes (256 pages of 512 bytes each) — MC9S08QE96: 98,304 bytes (192 pages of 512 bytes each) — MC9S08QE64: 65,536 bytes (128 pages of 512 bytes each) •...
Page 71 Flash Options Register (FOPT and NVOPT) The FOPT register holds all bits associated with the security of the MCU and ﬂash module. KEYEN Reset = Unimplemented or Reserved Figure 4-11. Flash Options Register (FOPT) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 72 Security”. 4.6.2.3 Flash Conﬁguration Register (FCNFG) The FCNFG register enables the ﬂash interrupts and gates the security backdoor writes. KEYACC Reset = Unimplemented or Reserved Figure 4-12. Flash Conﬁguration Register (FCNFG) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 73 Flash Protection Size — With FPOPEN set, the FPS bits determine the size of the protected ﬂash address FPS[6:0] range as shown in Table 4-18. Flash Protection Open FPOPEN 0 Flash array fully protected. 1 Flash array protected address range determined by FPS bits. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 74 7 Kbytes 0x79 0x0_E800–0x0_FFFF 6 Kbytes 0x7A 0x0_EC00–0x0_FFFF 5 Kbytes 0x7B 0x0_F000–0x0_FFFF 4 Kbytes 0x7C 0x0_F400–0x0_FFFF 3 Kbytes 0x7D 0x0_F800–0x0_FFFF 2 Kbytes 0x7E 0x0_FC00–0x0_FFFF 1 Kbyte 0x7F No Protection 0 Kbytes MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 75 FPVIOL ﬂag has no effect on FPVIOL. The FPVIOL ﬂag is cleared by writing a 1 to FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected. 1 Protection violation has occurred. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 76 FACCERR ﬂag in the FSTAT register. Table 4-21. Valid Flash Command List FCMD[6:0] NVM Command 0x05 Erase Verify 0x20 Program 0x25 Burst Program 0x40 Sector Erase 0x41 Mass Erase MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 77: Functional Description
FCLK < 150 kHz can destroy the ﬂash memory due to overstress. Setting FCDIV to a value such that FCLK > 200 kHz can result in incomplete programming or erasure of the ﬂash memory cells. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 78 A ﬂash block address must be in the erased state before being programmed. Cumulative programming of bits within a ﬂash block address is not allowed except for status ﬁeld updates required in EEPROM emulation applications. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 79 FBLANK ﬂag in the FSTAT register will be set if all addresses in the ﬂash array memory are veriﬁed to be erased. If any address in the ﬂash array memory is not erased, the erase verify operation will terminate and the FBLANK ﬂag in the FSTAT register will remain clear. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 80 1. Write to a ﬂash block address to start the command write sequence for the program command. The data written will be programmed to the address written. 2. Write the program command, 0x20, to the FCMD register. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 81 ﬁrst burst programming command is still in progress. This pipelined operation allows a time MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 82 FCBEF ﬂag in the FSTAT register has been set, greater than 50% faster programming time for the entire ﬂash array can be effectively achieved when compared to using the basic program command. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 83 Figure 4-18. Example Burst Program Command Flow 4.6.3.2.4 Sector Erase Command The sector erase operation will erase all addresses in a 1 Kbyte sector of ﬂash memory using an embedded algorithm. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 84 Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear FCBEF 0x80 Read: FSTAT register Bit Polling for FCCF Command Completion Set? Check EXIT Figure 4-19. Example Sector Erase Command Flow MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 85 ﬂash array. If the FPVIOL ﬂag is set in the FSTAT register, the user must clear the FPVIOL ﬂag before starting another command write sequence (see Section 4.6.2.5, “Flash Status Register (FSTAT)”). MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 86: Operating Modes
4.6.5 Flash Module Security The MC9S08QE128 Series includes circuitry to prevent unauthorized access to the contents of ﬂash and RAM memory. When security is engaged, ﬂash and RAM are considered secure resources. Direct-page registers, high-page registers, and the background debug controller are considered unsecured resources.
Page 87 The stored backdoor keys are unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the ﬂash module is determined by the ﬂash security byte. The MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 88: Resets
If a reset occurs while any ﬂash command is in progress, that command will be immediately aborted. The state of the ﬂash array address being programmed or the sector/block being erased is not guaranteed. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 89: Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt in the MC9S08QE128 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this reference manual. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
Page 90: Computer Operating Properly (Cop) Watchdog
When the bus clock source is selected, the COP counter does not increment while the system is in stop mode. The COP counter resumes as soon as the MCU exits stop mode. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 91: Interrupts
It is good programming practice to push H onto the stack at the start of the interrupt service routine (ISR) and restore it immediately before the RTI that is used to return from the ISR. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 92: Interrupt Stack Frame
When the MCU is in stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ pin (if enabled) can wake the MCU. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 93: Interrupt Vectors, Sources, And Local Masks
Higher-priority sources are located toward the bottom of the table. The high-order byte of the address for the interrupt service routine is located at the MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 94 CCR) is 0, the CPU will ﬁnish the current instruction; stack the PCL, PCH, X, A, and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 95 KBI1 and KBI2 share this vector, if both modules are enabled user should poll each ﬂag to determine pending interrupt. IIC1 and IIC2 share this vector, if both modules are enabled user should poll each ﬂag to determine pending interrupt. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 96: Low-Voltage Detect (Lvd) System
LVWV in SPMSC3. Peripheral Clock Gating The MC9S08QE128 Series includes a clock gating system to manage the bus clock sources to the individual peripherals. Using this system, the user can enable or disable the bus clock to each of the peripherals at the clock source, eliminating unnecessary clocks to peripherals which are not in use and thereby reducing the overall run and wait mode currents.
Page 97 When clocks are re-enabled to a peripheral, the peripheral registers need to be re-initialized by user software. In stop modes, the bus clock is disabled for all gated peripherals, regardless of the settings in SCGC1 and SCGC2. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 98: Reset, Interrupt, And System Control Registers And Control Bits
0 IRQ pin function is disabled. 1 IRQ pin function is enabled. IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred. IRQF 0 No IRQ request. 1 IRQ event detected. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 99: System Reset Status Register (Srs)
Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset entry will be cleared. Figure 5-3. System Reset Status (SRS) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 100: System Background Debug Force Reset Register (Sbdfr)
Reads always return 0x00. BDFR Reset: = Unimplemented or Reserved BDFR is writable only through serial background debug commands, not from user programs. Figure 5-4. System Background Debug Force Reset Register (SBDFR) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 101: System Options Register 1 (Sopt1)
When clear, the pin functions as one of its alternative functions. This pin defaults to its I/O port function following an MCU POR. 0 PTC4/TPM3CH4/RSTO pin functions as PTC4 or TPM3CH4. 1 PTC4/TPM3CH4/RSTO pin functions as RSTO. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 102: System Options Register 2 (Sopt2)
0 PTA5/IRQ/TCLK/RESET pin functions as PTA5, IRQ or TCLK. 1 PTA5/IRQ/TCLK/RESET pin functions as RESET. 5.8.5 System Options Register 2 (SOPT2) This high page register contains bits to conﬁgure MCU speciﬁc features on the MC9S08QE128 Series devices. COPCLKS SPI1PS ACIC2...
Page 103: System Device Identiﬁcation Register (Sdidh, Sdidl)
Bits 7:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect. Reserved Part Identiﬁcation Number — Each derivative in the HCS08 Family has a unique identiﬁcation number. The ID[11:8] MC9S08QE128 is hard coded to the value 0x015. See also ID bits in Table 5-9. Reset: = Unimplemented or Reserved Figure 5-8.
Page 104: System Power Management Status And Control 1 Register (Spmsc1)
Field Description Part Identiﬁcation Number — Each derivative in the HCS08 Family has a unique identiﬁcation number. The ID[7:0] MC9S08QE128 is hard coded to the value 0x015. See also ID bits in Table 5-8. 5.8.7 System Power Management Status and Control 1 Register...
Page 105: System Power Management Status And Control 2 Register (Spmsc2)
Low Power Wake Up on Interrupt — This bit controls whether or not the voltage regulator exits standby when LPWUI any active MCU interrupt occurs. 0 The voltage regulator will remain in standby on an interrupt. 1 The voltage regulator will exit standby on an interrupt. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 106: System Power Management Status And Control 3 Register (Spmsc3)
Low-Voltage Warning Acknowledge — The LVWF bit indicates the low voltage warning status. Writing a 1 to LVWACK LVWACK clears LVWF to a 0 if a low voltage warning is not present. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 107: System Clock Gating Control 1 Register (Scgc1)
When clocks are re-enabled to a peripheral, the peripheral registers need to be re-initialized by user software. TPM3 TPM2 TPM1 IIC2 IIC1 SCI2 SCI1 Reset: Figure 5-12. System Clock Gating Control 1 Register (SCGC1) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 108: System Clock Gating Control 2 Register (Scgc2)
When clocks are re-enabled to a peripheral, the peripheral registers need to be re-initialized by user software. ACMP SPI2 SPI1 Reset: = Unimplemented or Reserved Figure 5-13. System Clock Gating Control 2 Register (SCGC2) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 109 SPI1 Clock Gate Control — This bit controls the clock gate to the SPI1 module. SPI1 0 Bus clock to the SPI1 module is disabled. 1 Bus clock to the SPI1 module is enabled. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 110 Chapter 5 Resets, Interrupts, and General System Control MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 111: Parallel Input/Output Control
Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08QE128 has nine parallel I/O ports which include a total of 70 I/O pins and one output-only pin. Chapter 2, “Pins and Connections,” for more information about pin assignments and external hardware considerations of these pins.
Page 112: Pull-Up, Slew Rate, And Drive Strength
An output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 113: Port Data Set, Clear And Toggle Data Registers
Output Enable SET_Enable CLR_Enable TOGGLE_Enable PTxDn Module_Enable Output Data DATA Port Read Data Synchronizer Input Data BUSCLK Figure 6-2. Parallel I/O Block Diagram Equipped with SET/CLR Functionality: Ports C & E MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 114: Port Data Set Registers
This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header ﬁle normally is used to translate these names into the appropriate absolute addresses. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 115: Port A Registers
PTADD[7:0] PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 116 PTA pin. For port A pins that are conﬁgured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 117: Port B Registers
0 Low output drive strength selected for port A bit n. 1 High output drive strength selected for port A bit n. 6.5.2 Port B Registers Port B is controlled by the registers listed below. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 118 KBI. PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 Reset: Figure 6-10. Internal Pull Enable for Port B Register (PTBPE) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 119: Port C Registers
0 Low output drive strength selected for port B bit n. 1 High output drive strength selected for port B bit n. 6.5.3 Port C Registers Port C is controlled by the registers listed below. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 120 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn. 6.5.3.3 Port C Data Set Register (PTCSET) PTCSET7 PTCSET6 PTCSET5 PTCSET4 PTCSET3 PTCSET2 PTCSET1 PTCSET0 Reset: Figure 6-15. Port C Data Set Register (PTCSET) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 121 Toggle for Port C Bits — Writing any bit to one in this location will toggle the corresponding bit in the data PTCTOGn register. Writing a zero to any bit in this register has no effect. 0 Corresponding PTCDn maintains current value. 1 Corresponding PTCDn is inverted. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 122 PTC pin. For port C pins that are conﬁgured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 123: Port D Registers
0 Low output drive strength selected for port C bit n. 1 High output drive strength selected for port C bit n. 6.5.4 Port D Registers Port D is controlled by the registers listed below. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 124 KBI. PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 Reset: Figure 6-23. Internal Pull Enable for Port D Register (PTDPE) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 125: Port E Registers
0 Low output drive strength selected for port D bit n. 1 High output drive strength selected for port D bit n. 6.5.5 Port E Registers Port E is controlled by the registers listed below. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 126 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn. 6.5.5.3 Port E Data Set Register (PTESET) PTESET7 PTESET6 PTESET5 PTESET4 PTESET3 PTESET2 PTESET1 PTESET0 Reset: Figure 6-28. Port E Data Set Register (PTESET) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 127 The port E enable register (PTEPE) enables pull-ups on the corresponding PTE pin. In some cases, a pull-down device will be enabled if pull-downs are supported by an alternative pin function, such as KBI. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 128 PTE pin. For port E pins that are conﬁgured as inputs, these bits have no effect. 0 Output slew rate control disabled for port E bit n. 1 Output slew rate control enabled for port E bit n. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 129: Port F Registers
0 Low output drive strength selected for port E bit n. 1 High output drive strength selected for port E bit n. 6.5.6 Port F Registers Port F is controlled by the registers listed below. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 130 KBI. PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 Reset: Figure 6-36. Internal Pull Enable for Port F Register (PTFPE) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 131: Port G Registers
0 Low output drive strength selected for port F bit n. 1 High output drive strength selected for port F bit n. 6.5.7 Port G Registers Port G is controlled by the registers listed below. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 132 KBI. PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 Reset: Figure 6-41. Internal Pull Enable for Port G Register (PTGPE) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 133: Port H Registers
0 Low output drive strength selected for port G bit n. 1 High output drive strength selected for port G bit n. 6.5.8 Port H Registers Port H is controlled by the registers listed below. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 134 KBI. PTHPE7 PTHPE6 PTHPE5 PTHPE4 PTHPE3 PTHPE2 PTHPE1 PTHPE0 Reset: Figure 6-46. Internal Pull Enable for Port H Register (PTHPE) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 135: Port J Registers
0 Low output drive strength selected for port H bit n. 1 High output drive strength selected for port H bit n. 6.5.9 Port J Registers Port J is controlled by the registers listed below. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 136 KBI. PTJPE7 PTJPE6 PTJPE5 PTJPE4 PTJPE3 PTJPE2 PTJPE1 PTJPE0 Reset: Figure 6-51. Internal Pull Enable for Port J Register (PTJPE) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 137 PTJ pin. For port J pins that are conﬁgured as inputs, these bits have no effect. 0 Low output drive strength selected for port J bit n. 1 High output drive strength selected for port J bit n. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 138 Chapter 6 Parallel Input/Output Control MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 139: Keyboard Interrupt (S08Kbiv2)
Keyboard Interrupt (S08KBIV2) Introduction The keyboard interrupt (KBI) module provides up to eight independently enabled external interrupt sources. MC9S08QE128 Series devices contain two KBI modules, called KBI1 and KBI2. Each KBI module has up to eight interrupt sources. 7.1.1 KBI Clock Gating The bus clock to the KBI can be gated on and off using the KBI bit in SCGC2.
Page 140: Block Diagram
KBI1P3 KBI1P2 KBI1P1 KBI1P0 KBI1 Pin Table 7-2. KBI2 Pin Mapping PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Port Pin KBI2P7 KBI2P6 KBI2P5 KBI2P4 KBI2P3 KBI2P2 KBI2P1 KBI2P0 KBI2 Pin MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 141: Register Deﬁnition
KBI Detection Mode — KBIMOD (along with the KBIES bits) controls the detection mode of the KBI interrupt KBIMOD pins. 0 KBI pins detect edges only. 1 KBI pins detect both edges and levels. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 142: Kbi Interrupt Pin Select Register (Kbixpe)
A falling edge is detected when an enabled port input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 143: Edge Only Sensitivity
4. Enable the interrupt pins by setting the appropriate KBIPEn bits in KBIxPE. 5. Write to KBACK in KBIxSC to clear any false interrupts. 6. Set KBIE in KBIxSC to enable interrupts. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 144 Chapter 7 Keyboard Interrupt (S08KBIV2) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 145: Central Processor Unit (S08Cpuv4)
(BCD) operations • Efﬁcient bit manipulation instructions • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • STOP and WAIT instructions to invoke low-power operating modes MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 146: Programmer's Model And Cpu Registers
A or transferred to A where arithmetic and logical operations can then be performed. For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect on the contents of X. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 147: Stack Pointer (Sp)
For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 148 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow ﬂag. 0 No carry out of bit 7 1 Carry out of bit 7 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 149: Addressing Modes
Intel is LITTLE ENDIAN BIG ENDIAN located in the next memory location after that. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 150: Direct Addressing Mode (Dir)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 151: Special Operations
2. Set the I bit in the CCR. 3. Fetch the high-order half of the interrupt vector. 4. Fetch the low-order half of the interrupt vector. 5. Delay for one free bus cycle. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 152: Wait Mode Operation
CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in stop mode. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 153: Bgnd Instruction
1. The return value of the 8-bit PPAGE register is pulled from the stack. 2. The 16-bit return address is pulled from the stack and loaded into the PC. 3. The return PPAGE value is written to the PPAGE register. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 154 RTC. In this case, since RTC unstacks the PPAGE value as well as the return address, all accesses to the subroutine, even those made from the same page, must use CALL instructions. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 155: Hcs08 Instruction Set Summary
Half carry, bit 4 Interrupt mask, bit 3 Negative indicator, bit 2 Zero indicator, bit 1 Carry/borrow, bit 0 (carry out of bit 7) CCR activity notation – Bit not affected MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 156 The assembler will calculate the 8-bit signed offset and include it in the object code for this instruction. Address modes Inherent (no operands) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 157 Arithmetic Shift Right – – ASR oprx8,X ASR ,X ASR oprx8,SP 9E67 BCC rel Branch if Carry Bit Clear Branch if (C) = 0 – – – – – – REL 24 rr MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 158 – – – – – – BPL rel Branch if Plus Branch if (N) = 0 2A rr – – – – – – BRA rel Branch Always No Test 20 rr MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 159 (A) – (M) CMP oprx16,X Compare Accumulator ee ff – – (CCR Updated But Operands Not CMP oprx8,X with Memory Changed) CMP ,X CMP oprx16,SP 9ED1 ee ff CMP oprx8,SP 9EE1 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 160 Push (PCL); SP ← (SP) – 0x0001 – – – – – – JSR oprx16,X Jump to Subroutine ee ff Push (PCH); SP ← (SP) – 0x0001 JSR oprx8,X PC ← Unconditional Address JSR ,X MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 161 – – – – – – PSHH High) onto Stack Push X (Index Register Push (X); SP ← (SP) – 0x0001 – – – – – – PSHX Low) onto Stack MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 162 Store X (Low 8 Bits of ee ff M ← (X) 0 – – – STX oprx8,X Index Register) STX ,X in Memory STX oprx16,SP 9EDF ee ff STX oprx8,SP 9EEF MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 163 Transfer Index Reg. to SP Enable Interrupts; Wait I bit ← 0; Halt CPU – – 0 – – – WAIT for Interrupt Bus clock frequency is one-half of the CPU clock frequency. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 164 DIR to DIR IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Opcode in HCS08 Cycles Hexadecimal Instruction Mnemonic Addressing Mode Number of Bytes MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 165 Post Increment Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in 9E60 HCS08 Cycles Hexadecimal Instruction Mnemonic Addressing Mode Number of Bytes MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 166 Chapter 8 Central Processor Unit (S08CPUV4) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 167: Analog Comparator 3V (Acmpvlpv1)
Chapter 9 Analog Comparator 3V (ACMPVLPV1) Introduction MC9S08QE128 Series MCUs have two independent analog comparators (ACMPs), named ACMP1 and ACMP2. The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation).
Page 168: Interrupt Vectors
ACMP1 and ACMP2 share a single interrupt vector. When interrupts are enabled for both ACMPs, the ACF bit in ACMP1SC and ACMP2SC must be polled to determine which ACMP caused the interrupt. See Section 4.2, “Reset and Interrupt Vector Assignments,” for the ACMP interrupt vector assignment. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 169 48-pin and 32-pin packages PTG1 REFH REFL PTH0 and V pins are each internally connected to two pads in 32-pin package PTG0 Figure 9-1. MC9S08QE128 Series Block Diagram Highlighting ACMP Block and Pins MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 170: Features
ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP will continue to operate normally. 9.1.7 Block Diagram The block diagram for the Analog Comparator module is shown Figure 9-2. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 171: External Signal Description
Inverting analog input to the ACMP. (Minus input) ACMPx+ Non-inverting analog input to the ACMP. (Positive input) ACMPxO Digital output of the ACMP. Register Deﬁnition The ACMP includes one register: • An 8-bit status and control register MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 172: Acmpx Status And Control Register (Acmpxsc)
00 Encoding 0 — Comparator output falling edge 01 Encoding 1 — Comparator output rising edge 10 Encoding 2 — Comparator output falling edge 11 Encoding 3 — Comparator output rising or falling edge MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 173: Functional Description
ACF can be set on a rising edge of the comparator output, a falling edge of the comparator output, or either a rising or a falling edge (toggle). The comparator output can be read directly through ACO. The comparator output can be driven onto the ACMPxO pin using ACOPE. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 174 Analog Comparator (S08ACMPV3) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 175: Analog-To-Digital Converter (S08Adc12V1)
The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. Figure 10-1 shows the MC9S08QE128 Series with the ADC module and pins highlighted. NOTE Ignore any references to stop1 low-power mode in this chapter, because the MC9S08QE128 device does not support it.
Page 176 48-pin and 32-pin packages PTG1 REFH REFL PTH0 and V pins are each internally connected to two pads in 32-pin package PTG0 Figure 10-1. MC9S08QE128 Series Block Diagram Highlighting ADC Block and Pins MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 177: Module Conﬁgurations
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 10.1.2 Module Conﬁgurations This section provides device-speciﬁc information for conﬁguring the ADC on the MC9S08QE128 Series. 10.1.2.1 Channel Assignments The ADC channel assignments for the MC9S08QE128 Series devices are shown in Table 10-1. Reserved channels convert to an unknown value.
Page 178 V the cold slope value is applied in Equation 10-1. If V TEMP25 TEMP TEMP25 TEMP less than V the hot slope value is applied in Equation 10-1. TEMP25 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 179: Features
Selectable asynchronous hardware conversion trigger. • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value. 10.1.4 Block Diagram Figure 10-2 provides a block diagram of the ADC module MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 180: External Signal Description
The ADC module supports up to 28 separate analog inputs. It also requires four supply/reference/ground connections. Table 10-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs High reference voltage REFH Low reference voltage REFL Analog power supply DDAD Analog ground SSAD MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 181: Analog Power
This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 182 Figure 10-4. Input Channel Select ADCH Input Select ADCH Input Select 00000 10000 AD16 00001 10001 AD17 00010 10010 AD18 00011 10011 AD19 00100 10100 AD20 00101 10101 AD21 00110 10110 AD22 00111 10111 AD23 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 183: Status And Control Register 2 (Adcsc2)
ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 184: Data Result High Register (Adcrh)
If ADCRL is not read until the after next conversion is completed, then the intermediate conversion results will be lost. In 8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data in ADCRL becomes invalid. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 185: Compare Value High Register (Adccvh)
Figure 10-9. Compare Value Low Register(ADCCVL) 10.3.7 Conﬁguration Register (ADCCFG) ADCCFG is used to select the mode of operation, clock source, clock divide, and conﬁgure for low power or long sample time. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 186 Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ 8 Table 10-7. Conversion Modes MODE Mode Description 8-bit conversion (N=8) 12-bit conversion (N=12) 10-bit conversion (N=10) Reserved MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 187: Pin Control 1 Register (Apctl1)
1 AD3 pin I/O control disabled ADC Pin Control 2 — ADPC2 is used to control the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 188: Pin Control 2 Register (Apctl2)
1 AD11 pin I/O control disabled ADC Pin Control 10 — ADPC10 is used to control the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 189: 10Pin Control 3 Register (Apctl3)
1 AD19 pin I/O control disabled ADC Pin Control 18 — ADPC18 is used to control the pin associated with channel AD18. ADPC18 0 AD18 pin I/O control enabled 1 AD18 pin I/O control disabled MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 190: Functional Description
Whichever clock is selected, its frequency must fall within the speciﬁed frequency range for ADCK. If the available clocks are too slow, the ADC will not perform according to speciﬁcations. If the available clocks MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 191: Input Select And Pin Control
In software triggered operation, continuous conversions begin after ADCSC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 192 (3.5 ADCK cycles) and long (23.5 ADCK cycles) sample times.When sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 193 Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles NOTE The ADCK frequency must be between f minimum and f ADCK ADCK maximum to meet ADC speciﬁcations. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 194: Automatic Compare Function
ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode. After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 195: Mcu Stop1 And Stop2 Mode Operation
1. Update the conﬁguration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power conﬁguration. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 196 Holds compare value when compare function enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 197: Application Information
SSAD as their corresponding MCU digital supply (V and V ) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 198 The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high. For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 199: Sources Of Error
Place a 0.01 μF capacitor (C • ) on the selected input channel to V or V (this will REFL SSAD improve noise issues but will affect sample rate based on the external analog source resistance). MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 200 • Total unadjusted error (TUE) — This error is deﬁned as the difference between the actual transfer function and the ideal straight-line transfer function, and therefore includes all forms of error. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 201 Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 202 12-bit Analog-to-Digital Converter (S08ADCV1) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 203: Internal Clock Source (S08Icsv3)
EREFSTEN. To disable the oscillator in stop2, switch the ICS into FBI or FEI mode before executing the STOP instruction. Figure 11-1 shows the MC9S08QE128 Series block diagram with the ICS highlighted. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 204 48-pin and 32-pin packages PTG1 REFH REFL PTH0 and V pins are each internally connected to two pads in 32-pin package PTG0 Figure 11-1. MC9S08QE128 Series Block Diagram Highlighting ICS Block and Pins MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 205: Features
Three selectable digitally controlled oscillators (DCO) optimized for different frequency ranges. • Option to maximize output frequency for a 32768 Hz external reference clock source. 11.1.4 Block Diagram Figure 11-2 is the ICS block diagram. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 206: Modes Of Operation
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied from the FLL. MC9S08QE128 MCU Series Reference Manual, Rev. 1.11 Freescale Semiconductor...
Page 207: External Signal Description
ICS registers. Table 11-1. ICS Register Summary Name ICSC1 CLKS RDIV IREFS IRCLKEN IREFSTEN ICSC2 BDIV RANGE EREFS ERCLKEN EREFSTEN ICSTRM TRIM DRST IREFST CLKST OSCINIT ICSSC DMX32 FTRIM MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 208: Ics Control Register 1 (Icsc1)
1 Internal reference clock stays enabled in stop if IRCLKEN is set before entering stop 0 Internal reference clock is disabled in stop Table 11-3. Reference Divide Factor RDIV RANGE=0 RANGE=1 1024 Reserved Reserved Reset default MC9S08QE128 MCU Series Reference Manual, Rev. 1.11 Freescale Semiconductor...
Page 209: Ics Control Register 2 (Icsc2)
Reset: Note: TRIM is loaded during reset from a factory programmed location when not in BDM mode. If in a BDM mode, a default value of 0x80 is loaded. Figure 11-5. ICS Trim Register (ICSTRM) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 210: Ics Status And Control (Icssc)
IREFS bit due to internal synchronization between clock domains. 0 Source of reference clock is external clock. 1 Source of reference clock is internal clock. MC9S08QE128 MCU Series Reference Manual, Rev. 1.11 Freescale Semiconductor...
Page 211 31.25 - 39.0625 kHz 1536 48 - 60 Mhz 32.768 kHz 1824 59.77 Mhz Reserved The resulting bus clock frequency should not exceed the maximum speciﬁed bus clock frequency of the device. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 212: Functional Description
The FLL loop will lock the frequency to the FLL factor times the internal reference frequency. The ICSLCLK is available for BDC communications, and the internal reference clock is enabled. MC9S08QE128 MCU Series Reference Manual, Rev. 1.11 Freescale Semiconductor...
Page 213 RDIV bits are written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz. • BDM mode is active or LP bit is written to 0. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 214: Mode Switching
DCO the FLL remains unlocked for several reference cycles. Once the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the DRST bits. MC9S08QE128 MCU Series Reference Manual, Rev. 1.11 Freescale Semiconductor...
Page 215: Bus Frequency Divider
ICSTRM register and ICS FTRIM register during any reset initialization. For ﬁner precision, the user can trim the internal oscillator in the application and set the FTRIM bit accordingly. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 216: External Reference Clock
The ICS presents the low range DCO output clock divided by two as ICSLCLK for use as a clock source for BDC communications. ICSLCLK is not available in FLL bypassed internal low power (FBILP) and FLL bypassed external low power (FBELP) modes. MC9S08QE128 MCU Series Reference Manual, Rev. 1.11 Freescale Semiconductor...
Page 217: Inter-Integrated Circuit (S08Iicv2)
12.1.2 Interrupt Vectors For MC9S08QE128 Series MCUs with two IICs, both IICs share a single interrupt vector. When interrupts are enabled for both IICs, the IICF bit must be polled in the IIC1S and IIC2S registers to determine which IIC caused the interrupt. See Section 4.2, “Reset and Interrupt Vector...
Page 218 48-pin and 32-pin packages PTG1 REFH REFL PTH0 and V pins are each internally connected to two pads in 32-pin package PTG0 Figure 12-1. MC9S08QE128 Series Block Diagram Highlighting the IIC Modules MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 219: Features
• Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The STOP instruction does not affect IIC register states. Stop2 will reset the register contents. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 220: Block Diagram
SCL — Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 12.2.2 SDA — Serial Data Line The bidirectional SDA is the serial data line of the IIC system. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 221: Register Deﬁnition
Slave Address — The AD[7:1] ﬁeld contains the slave address to be used by the IIC module. This ﬁeld is used AD[7:1] on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 222: Iic Frequency Divider Register (Iicxf)
ICR and MULT selections to achieve an IIC baud rate of 100kbps. Hold times (μs) MULT SCL Start SCL Stop 0x00 3.500 4.750 5.125 0x07 2.500 4.250 5.125 0x0B 2.250 4.000 5.250 0x14 2.125 4.000 5.250 0x18 1.125 3.000 5.500 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 223 Value (hex) Divider Value Value Value Value Value 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 224: Iic Control Register (Iicxc1)
Repeat START — Writing a 1 to this bit will generate a repeated START condition provided it is the current RSTA master. This bit will always be read as a low. Attempting a repeat at the wrong time will result in loss of arbitration. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 225: Iic Status Register (Iicxs)
If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received. 1 No acknowledge received. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 226: Iic Data I/O Register (Iicxd)
In master transmit mode, the ﬁrst byte of data written to IICxD following assertion of MST is used for the address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required R/W bit (in position bit 0). MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 227: Iic Control Register 2 (Iicxc2)
Slave Address — The AD[10:8] ﬁeld contains the upper three bits of the slave address in the 10-bit address AD[10:8] scheme. This ﬁeld is only valid when the ADEXT bit is set. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 228: Functional Description
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W START CALLING ADDRESS READ/ REPEATED NEW CALLING ADDRESS STOP READ/ SIGNAL START SIGNAL WRITE WRITE SIGNAL Figure 12-9. IIC Bus Transmission Signals MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 229 In either case, the data transfer is aborted and the master does one of two things: • Relinquishes the bus by generating a STOP signal. • Commences a new calling by generating a repeated START signal. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 230 There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The ﬁrst device to complete its high period pulls the SCL line low again. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 231 SCL low the slave can drive SCL low for the required period and then release it. If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 232: 10-Bit Address
After the master-receiver has sent the ﬁrst byte of the 10-bit address, the slave-transmitter will see an IIC interrupt. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as valid data. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 233: General Call Address
The IIC module asserts this interrupt when it loses the data arbitration process and the ARBL bit in the status register is set. Arbitration is lost in the following circumstances: MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 234 A repeated START cycle is requested in slave mode. • A STOP condition is detected when the master did not request it. This bit must be cleared by software by writing a 1 to it. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 235: Initialization/Application Information
RXAK IICS Module status ﬂags DATA IICD Data register; Write to transmit IIC data read to read IIC data IICC2 GCAEN ADEXT AD10 Address conﬁguration Figure 12-11. IIC Module Quick Start MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 236 2. When 10-bit addressing is used to address a slave, the slave will see an interrupt following the ﬁrst byte of the extended address. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer Figure 12-12. Typical IIC Interrupt Routine MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 237: Real-Time Counter (S08Rtcv1)
13.1.3.1 RTC Status after Stop2 Wakeup The registers associated with the RTC are unaffected after a stop2 wakeup. 13.1.3.2 Clocks in Stop Modes In the MC9S08QE128 Series, LPO and OSCOUT can be used in stop2 and stop3. IRCLK is available only in stop3. 13.1.4 RTC Clock Gating The bus clock to the RTC can be gated on and off with SCGC2[RTC].
Page 238: Interrupt Vector
Chapter 13 Real-Time Counter (S08RTCV1) 13.1.5 Interrupt Vector Section 4.2, “Reset and Interrupt Vector Assignments,” for the RTC interrupt vector assignment. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 239 48-pin and 32-pin packages PTG1 REFH REFL PTH0 and V pins are each internally connected to two pads in 32-pin package PTG0 Figure 13-1. MC9S08QE128 Block Diagram Highlighting RTC Block and Pins MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 240: Features
The RTC suspends all counting during active background mode until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as the RTCMOD register is not written and the RTCPS and RTCLKS bits are not altered. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 241: Block Diagram
RTC registers.This section refers to registers and control bits only by their names and relative address offsets. Table 13-1 is a summary of RTC registers. Table 13-1. RTC Register Summary Name RTCSC RTIF RTCLKS RTIE RTCPS Clock Source Select RTCCNT RTCCNT RTCMOD RTCMOD MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 242: Rtc Status And Control Register (Rtcsc)
Table 13-3. Changing the prescaler value clears the prescaler and RTCCNT counters. Reset clears RTCPS to 0000. Table 13-3. RTC Prescaler Divide-by values RTCPS RTCLKS[0] 5x10 2x10 5x10 2x10 5x10 2x10 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 243: Rtc Counter Register (Rtccnt)
RTIF status bit. A value of 0x00 sets the RTIF bit on each rising edge of the prescaler output. Writing to RTCMOD resets the prescaler and the RTCCNT counters to 0x00. Reset sets the modulo to 0x00. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 244: Functional Description
20 ms 0.5 ms 0.625 s 1101 0.1 s 50 ms 3.125 ms 1.5625 s 1110 0.5 s 0.1 s 15.625 ms 3.125 s 1111 0.2 s 31.25 ms 6.25 s MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 245: Rtc Operation Example
For accuracy without adjustments at the expense of additional power consumption, the external clock (ERCLK) or the internal clock (IRCLK) can be selected with appropriate prescaler and modulo values. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 246 /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 247: Serial Communications Interface (S08Sciv4)
Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction Figure 14-1 shows the MC9S08QE128 Series block diagram with the SCI highlighted. NOTE Ignore any references to stop1 low-power mode in this chapter, because the MC9S08QE128 device does not support it. 14.1.1 SCI Clock Gating The bus clock to SCI1 and SCI2 can be gated on and off using the SCGC1[SCI1,SCI2] bits, respectively.
Page 248 48-pin and 32-pin packages PTG1 REFH REFL PTH0 and V pins are each internally connected to two pads in 32-pin package PTG0 Figure 14-1. MC9S08QE128 Series Block Diagram Highlighting SCI Block and Pins MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 249 Rx/Tx pin Tx data path direction in polarity single-wire mode R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 SCIxD Read: Rx data; write: Tx data Figure 14-2. SCI Module Quick Start MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 250: Features
Modes of Operation Section 14.3, “Functional Description,” For details concerning SCI operation in these modes: • 8- and 9-bit data modes • Stop mode operation • Loop mode • Single-wire mode MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 251: Block Diagram
RATE CLOCK SHIFT DIRECTION TXINV PARITY GENERATION SCI CONTROLS TxD TO TxD TRANSMIT CONTROL PIN LOGIC TxD DIRECTION TXDIR BRK13 TDRE Tx INTERRUPT REQUEST TCIE Figure 14-3. SCI Transmitter Block Diagram MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 252 WAKEUP RWUID LOGIC ACTIVE EDGE DETECT RDRF IDLE ILIE Rx INTERRUPT REQUEST LBKDIF LBKDIE RXEDGIF RXEDGIE ORIE FEIE ERROR INTERRUPT REQUEST NEIE PARITY CHECKING PEIE Figure 14-4. SCI Receiver Block Diagram MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 253: Register Deﬁnition
SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 14-2. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 254: Sci Control Register 1 (Scixc1)
0 Normal — start + 8 data bits (LSB ﬁrst) + stop. 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (LSB ﬁrst) + 9th data bit + stop. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 255: Sci Control Register 2 (Scixc2)
1 Hardware interrupt requested when RDRF ﬂag is 1. Idle Line Interrupt Enable (for IDLE) ILIE 0 Hardware interrupts from IDLE disabled (use polling). 1 Hardware interrupt requested when IDLE ﬂag is 1. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 256: Sci Status Register 1 (Scixs1)
This register has eight read-only status ﬂags. Writes have no effect. Special software sequences (which do not involve writing to this register) are used to clear these status ﬂags. TDRE RDRF IDLE Reset = Unimplemented or Reserved Figure 14-9. SCI Status Register 1 (SCIxS1) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 257 ﬂag NF will be set at the same time as the ﬂag RDRF gets set for the character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No noise detected. 1 Noise detected in the received character in SCIxD. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 258: Sci Status Register 2 (Scixs2)
0 Break character is transmitted with length of 10 bit times (11 if M = 1) 1 Break character is transmitted with length of 13 bit times (14 if M = 1) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 259: Sci Control Register 3 (Scixc3)
(LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 260: Sci Data Register (Scixd)
The following describes each of the blocks of the SCI. 14.3.1 Baud Rate Generation As shown in Figure 14-13, the clock source for the SCI baud rate generator is the bus-rate clock. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 261: Transmitter Functional Description
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete ﬂag and enters an idle mode, with TxD high, waiting for more characters to transmit. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 262: Receiver Functional Description
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (RDRF) status MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 263 ﬂags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 264: Interrupts And Status Flags
If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 265: Additional Sci Functions
Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 266 In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 267: Serial Peripheral Interface (S08Spiv3)
Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.1 Introduction Figure 15-1 shows the MC9S08QE128 Series block diagram with the SPI highlighted. NOTE Ignore any references to stop1 low-power mode in this chapter, because the MC9S08QE128 device does not support it. 15.1.1...
Page 268 48-pin and 32-pin packages PTG1 REFH REFL PTH0 and V pins are each internally connected to two pads in 32-pin package PTG0 Figure 15-1. MC9S08QE128 Block Diagram Highlighting SPI Block and Pins MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 269: Features
(SS pin). In this system, the master device has conﬁgured its SS pin as an optional slave select output. MASTER SLAVE MOSI MOSI SPI SHIFTER SPI SHIFTER MISO MISO SPSCK SPSCK CLOCK GENERATOR Figure 15-2. SPI System Connections MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 270 In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 271: Spi Baud Rate Generation
(SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal SPI master mode bit-rate clock. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 272: External Signal Description
I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select output (SSOE = 1). MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 273: Modes Of Operation
SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). SPTIE 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 274: Spi Control Register 2 (Spixc2)
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not implemented and always read 0. MODFEN BIDIROE SPISWAI SPC0 Reset = Unimplemented or Reserved Figure 15-6. SPI Control Register 2 (SPIxC2) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 275: Spi Baud Rate Register (Spixbr)
Table 15-6. The input to this divider comes from the SPI baud rate prescaler (see Figure 15-4). The output of this divider is the SPI bit rate clock for master mode. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 276: Spi Status Register (Spixs)
This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0. Writes have no meaning or effect. SPRF SPTEF MODF Reset = Unimplemented or Reserved Figure 15-8. SPI Status Register (SPIxS) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 277: Spi Data Register (Spixd)
Data may be read from SPIxD any time after SPRF is set and before another transfer is ﬁnished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 278: Functional Description
CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 279 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB ﬁrst and LSB ﬁrst lines show the order of SPI data bits depending on the setting MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 280 MOSI and MISO outputs of the master and slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between transfers. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 281: Spi Interrupts
MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIxC1). User software should verify the error condition has been corrected before changing the SPI back to master mode. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 282 Serial Peripheral Interface (S08SPIV3) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 283: Timer/Pulse-Width Modulator (S08Tpmv3)
Timer/Pulse-Width Modulator (S08TPMV3) 16.1 Introduction Figure 16-1 shows the MC9S08QE128 Series block diagram with the TPM highlighted. 16.1.1 ACMP/TPM Conﬁguration Information The ACMP modules can be conﬁgured to connect the output of the analog comparator to a TPM input capture channel 0 by setting the corresponding SOPT2[ACICx] bit. With ACICx set, the TPMxCH0 pin is not available externally regardless of the conﬁguration of the TPMx module.
Page 284 48-pin and 32-pin packages PTG1 REFH REFL PTH0 and V pins are each internally connected to two pads in 32-pin package PTG0 Figure 16-1. MC9S08QE128 Series Block Diagram Highlighting TPM Block and Pins MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 285: Features
MCU pin. The output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions). MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 286: Block Diagram
Software can read the counter value at any time without affecting the counting sequence. Any write to either half of the TPMxCNT counter resets the counter, regardless of the data value written. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 287 CH1IE MS1B MS1A Up to 8 channels ELS7B ELS7A PORT CHANNEL 7 TPMxCH7 LOGIC 16-BIT COMPARATOR TPMxC7VH:TPMxC7VL CH7F INTER- 16-BIT LATCH RUPT LOGIC CH7IE MS7B MS7A Figure 16-2. TPM Block Diagram MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 288: Signal Description
TPM, refer to full-chip documentation for a speciﬁc derivative for more details about the interaction of TPM pin functions and general purpose I/O controls including port data, data direction, and pullup controls. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 289 16-bit channel value register matches the timer counter. When the output compare toggle mode is initially selected, the previous value on the pin is driven out until the next output compare event—then the pin is toggled. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 290 CHnF BIT TOF BIT Figure 16-3. High-True Pulse of an Edge-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF BIT TOF BIT Figure 16-4. Low-True Pulse of an Edge-Aligned PWM MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 291 CHnF BIT TOF BIT Figure 16-5. High-True Pulse of a Center-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF BIT TOF BIT Figure 16-6. Low-True Pulse of a Center-Aligned PWM MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 292: Register Deﬁnition
TPM system. The new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 293: Tpm-Counter Registers (Tpmxcnth:tpmxcntl)
TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write. Bit 15 Bit 8 Any write to TPMxCNTH clears the 16-bit counter Reset Figure 16-8. TPM Counter Register High (TPMxCNTH) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 294: Tpm Counter Modulo Registers (Tpmxmodh:tpmxmodl)
BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active. Bit 15 Bit 8 Reset Figure 16-10. TPM Counter Modulo Register High (TPMxMODH) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 295: Tpm Channel N Status And Control Register (Tpmxcnsc)
Mode select B for TPM channel n. When CPWMS=0, MSnB=1 conﬁgures TPM channel n for edge-aligned PWM MSnB mode. Refer to the summary of channel mode and setup controls in Table 16-6. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 296: Tpm Channel Value Registers (Tpmxcnvh:tpmxcnvl)
These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel registers are cleared by reset. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 297 BDM is active. The values written to the channel register while BDM is active are used for PWM & output compare operation once normal execution resumes. Writes to the channel MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 298: Functional Description
(writing 00 to the CLKSB:CLKSA ﬁeld) does not affect the values in the counter or other timer registers. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 299 This corresponds to the end of a PWM period (the 0x0000 count value corresponds to the center of a period). MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 300: Channel Mode Selection
With the output-compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel-value registers of an output-compare channel, the TPM can set, clear, or toggle the channel pin. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 301 If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 302 Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined up at the same system clock edge. This type of PWM is also required for some types of motor drives. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 303: Reset Overview
If the channel is conﬁgured for output compare or PWM modes, the interrupt ﬂag is set each time the main timer counter matches the value in the 16-bit channel value register. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 304: Description Of Interrupt Operation
PWM (CPWMS=0), TOF gets set when the timer counter changes from the terminal count (the value in the modulo register) to 0x0000. This case corresponds to the normal meaning of counter overﬂow. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 305 ﬂag is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value register. The ﬂag is cleared by the two-step sequence described Section 16.6.2, “Description of Interrupt Operation.” MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 306 Timer/PWM Module (S08TPMV3) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 307: Development Support
The method for forcing active background mode depends on the speciﬁc HCS08 derivative. For the MC9S08QE128 Series, you can force active background after a power-on reset by holding the BKGD pin low as the device exits the reset condition. You can also force active background by driving BKGD low immediately after a serial background command that writes a one to the BDFR bit in the SBDFR register.
Page 308: Features
However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 309: Bkgd Pin Description
MSB ﬁrst at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 310 HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES EARLIEST START OF NEXT BIT SYNCHRONIZATION TARGET SENSES BIT LEVEL UNCERTAINTY PERCEIVED START OF BIT TIME Figure 17-2. BDC Host-to-Target Serial Bit Timing MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 311 PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure 17-3. BDC Target-to-Host Serial Bit Timing (Logic 1) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 312 SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure 17-4. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 313: Bdc Commands
8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) RBKP 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 314 Increment H:X by one, then write memory byte WRITE_NEXT_WS Active BDM 51/WD/d/SS located at H:X. Also report status. The SYNC command is a special operation that does not have a command code. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 315: Bdc Hardware Breakpoint
The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. 17.3 Register Deﬁnition This section contains the descriptions of the BDC registers and control bits. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 316: Bdc Registers And Control Bits
WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 317 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC CLKSW clock source. 0 Alternate BDC clock source 1 MCU bus clock MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 318: System Background Debug Force Reset Register (Sbdfr)
0 Memory access did not conﬂict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode Data Valid Failure Status — This status bit is not used in the MC9S08QE128 Series because it does not have any slow access memory.
Page 319 Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 320 Development Support MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 321: Debug Module (Dbg) (128K)
— Source address of conditional branches taken — Destination address of indirect JMP and JSR instruction — Destination address of interrupts, RTI, RTC, and RTS instruction — Data associated with Event B trigger modes MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 322: Modes Of Operation
1. In 64K versions of this module there are only 16 address lines [15:0], there are no core_cpu_aob_14_t2, core_cpu_aob_15_t2, core_ppage_t2[2:0], and ppage_sel signals. Figure 18-1. DBG Block Diagram 18.2 Signal Description The DBG module contains no external signals. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 323: Memory Map And Registers
Debug Control Register (DBGC) Read/write Base + $000D Debug Trigger Register (DBGT) Read/write Base + $000E Debug Status Register (DBGS) Read only Base + $000F Debug FIFO Count Register (DBGCNT) Read only MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 324 Bit 1 Bit 0 DBGCAX RWAEN PAGSEL bit-16 DBGCBX RWBEN PAGSEL bit-16 DBGCCX RWCEN PAGSEL bit-16 DBGFX PPACC bit-16 DBGC DBGEN BRKEN LOOP1 DBGT TRGSEL BEGIN TRG[3:0] DBGS ARMF DBGCNT CNT[3:0] MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 325: Register Descriptions
Figure 18-3. Debug Comparator A Low Register (DBGCAL) In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 326 Module Base + 0x0003 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 or non- end-run Reset end-run Figure 18-5. Debug Comparator B Low Register (DBGCBL) MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 327 [15:8] to a logic 1 or logic 0. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 328 = Unimplemented or Reserved Figure 18-8. Debug FIFO High Register (DBGFH) In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 329 FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX and DBGFH so it is not necessary to read them before reading DBGFL. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 330 Comparator A will compare the core address bus bit 16 to a logic 1 or logic 0. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 331 Comparator B will compare the core address bus bit 16 to a logic 1 or logic 0. This bit is not used in full modes where comparator B is used to match the data value. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 332 Comparator C will compare the core address bus bit 16 to a logic 1 or logic 0. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 333 1 The information in the corresponding FIFO word is a 17-bit ﬂash address with PPAGE[2:0] in the three most signiﬁcant bits and CPU address[13:0] in the 14 least signiﬁcant bits Extended Address Bit 16 — This bit is the most signiﬁcant bit of the 17-bit core address. Bit 16 MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 334 COF address with the address in comparator C. If these addresses match, override the FIFO capture and do not increment the FIFO count. If the address does not match comparator C, capture the COF address, including the PPACC indicator, into the FIFO and into comparator C. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 335 A Then B 0011 Event Only B 0100 A Then Event Only B 0101 A And B (Full Mode) 0110 A And Not B (Full mode) 0111 Inside Range 1000 Outside Range MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 336 While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. See Section 18.4.4.2, “Arming the DBG Module” for more information. 0 Debugger not armed 1 Debugger armed MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 337 1 word valid 0010 2 words valid 0011 3 words valid 0100 4 words valid 0101 5 words valid 0110 6 words valid 0111 7 words valid 1000 8 words valid MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 338: Functional Description
FIFO. This bit indicates whether the COF address was a paged 17-bit program address using the PPAGE mechanism (PPACC=1) or a 17-bit CPU address that resulted from an unpaged CPU access. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 339: Breakpoints
With the TRGSEL bit cleared a comparator match is all that is necessary for a trigger condition to be met. NOTE If the TRGSEL is set, the address stored in the comparator match address registers must be an opcode address for the trigger to occur. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 340: Trigger Break Control (Tbc)
FIFO is ﬁlled in begin-trigger mode. In the case of an end-trace where DBGEN=1 and BEGIN=0, ARM and ARMF are cleared by any reset to MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 341 For Breakpoint tagging operation with an end-trigger type trace, only matches from Comparator A will be used to determine if the Breakpoint conditions are met and Comparator B matches will be ignored. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 342 Start FIFO at trigger address, force CPU breakpoint when FIFO full Do not use Start FIFO at trigger opcode (No CPU breakpoint - keep running) Start FIFO at trigger opcode, force CPU breakpoint when FIFO full Do not use MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 343: Fifo
The data stored in the FIFO can be read using BDM commands provided the DBG module is enabled and not armed (DBGEN=1 and ARM=0). The FIFO data is read out ﬁrst-in-ﬁrst-out. By reading the CNT bits MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 344: Interrupt Priority
POR, the DBG module controls are initialized to start a begin trace run starting from when the reset vector is fetched. The conditions for the default begin trace run are: MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...
Page 345: Interrupts
DBGT=0x40 to select a force-type trigger, a BEGIN trigger, and A-only trigger mode 18.6 Interrupts The DBG contains no interrupt source. 18.7 Electrical Speciﬁcations The DBG module contain no electrical speciﬁcations. MC9S08QE128 MCU Series Reference Manual, Rev. 2 Freescale Semiconductor...

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ROHS MC9S08QE128 Reference Manual

Section Number Title Page

Chapter 1 Device Overview

Chapter 2 Pins and Connections

Chapter 3 Modes of Operation

Chapter 4 Memory

Chapter 5

Chapter 6 Parallel Input/Output Control

Chapter 7 Keyboard Interrupt (S08KBIV2)

Chapter 8 Central Processor Unit (S08CPUV4)

Chapter 9 Analog Comparator 3V (ACMPVLPV1)

Chapter 10 Analog-To-Digital Converter (S08ADC12V1)

Chapter 11 Internal Clock Source (S08ICSV3)

Chapter 12 Inter-Integrated Circuit (S08IICV2)

Chapter 13 Real-Time Counter (S08RTCV1)

Chapter 14 Serial Communications Interface (S08SCIV4)

Chapter 15 Serial Peripheral Interface (S08SPIV3)

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Summary of Contents for ROHS MC9S08QE128