Port Data Set, Clear And Toggle Data Registers - ROHS MC9S08QE128 Reference Manual

sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the MCU are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this, the EMC emissions may be affected by enabling pins as high drive.
6.3

Port Data Set, Clear and Toggle Data Registers

The Port Data Set, Clear and Toggle registers provide an alternate method for setting and clearing
individual port I/O pins within a single port. Only port C and port E have data set, clear and toggle registers.
Figure 6-2 should be contrasted with
to the port cell. SET_Enable, CLR_Enable, and Toggle_Enable will be set to 1 when the user writes to the
Data Set, Clear or Toggle register, respectively. The bit pattern on the peripheral bus port is then used to
perform the requested function on the port data register.
SET_Enable
CLR_Enable
TOGGLE_Enable
Module_Enable
DATA
Figure 6-2. Parallel I/O Block Diagram Equipped with SET/CLR Functionality: Ports C & E
Freescale Semiconductor
Figure 6-1 to see the effects of adding Set/Clear/Toggle functionality
Port Read
Data
BUSCLK
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Chapter 6 Parallel Input/Output Control
PTxDDn
Output Enable
D Q
PTxDn
D Q
1
0 Synchronizer
Output Data
Input Data
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