Active Background Mode; Wait Mode - ROHS MC9S08QE128 Reference Manual

Chapter 3 Modes of Operation
3.5

Wait Mode

Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
3.5.1 Low Power Wait Mode (LPWait)
Low power wait mode is entered by executing a WAIT instruction while the MCU is in low power run
mode. In the low power wait mode, the on-chip voltage regulator remains in its standby state as in the low
power run mode. In this state, the power consumption is reduced to a minimum that still allows most
modules to maintain functionality. Power consumption is reduced the most by disabling the clocks to all
unused peripherals by clearing the corresponding bits in the SCGC register.
The same restrictions from the low power run mode apply to low power wait mode.
3.5.1.1 Interrupts in Low Power Wait Mode
If the LPWUI bit is set when the WAIT instruction is executed, then the voltage regulator will return to full
regulation when wait mode is exited. The ICS can be set for full speed immediately in the interrupt service
routine.
If the LPWUI bit is clear when the WAIT instruction is executed, an interrupt will return the device to low
power run mode.
If the LPWUI bit is set when the WAIT instruction is executed, an interrupt will return the device to normal
run mode with full regulation and the LPR and LPRS bits will be cleared.
3.5.1.2 Resets in Low Power Wait Mode
Any reset will exit low power wait mode, clear LPR and LPRS bit, and return the device to normal run
mode.
3.6 Stop Modes
Either stop2 or stop3 is entered upon execution of a STOP instruction when the STOPE bit in the system
option 1 register (SOPT1) is set. In both stop modes, the bus and CPU clocks are halted. In stop3 the
regulator is in standby. In stop2 the regulator is in partial powerdown. The ICS module can be configured
to leave the reference clocks running. See
information.
42
Chapter 11, "Internal Clock Source
MC9S08QE128 MCU Series Reference Manual, Rev. 2
(S08ICSV3)" for more
Freescale Semiconductor