System Options Register 1 (Sopt1) - ROHS MC9S08QE128 Reference Manual

Field
0 Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.To enter user mode, PTA4/ACMPO/BKGD/MS must be high immediately after
issuing WRITE_BYTE command. To enter BDM, PTA4/ACMPO/BKGD/MS must be low immediately after issuing
WRITE_BYTE command. See the data sheet for more information.
5.8.4

System Options Register 1 (SOPT1)

This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. SOPT1 should be written during the user's reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
7
R
COPE
W
Reset: 1
POR: 1
LVR: 1
= Unimplemented or Reserved
1
u = unaffected
Field
7 COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.
COPE 0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6 COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. COPT along with
COPT COPCLKS in SOPT2 defines the COP timeout period.
0 Short timeout period selected.
1 Long timeout period selected.
5 Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
STOPE program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
2 RSTO Pin Enable — This write-once bit when set enables the PTC4/TPM3CH4/RSTO pin to function as RSTO.
RSTOPE When clear, the pin functions as one of its alternative functions. This pin defaults to its I/O port function following
an MCU POR.
0 PTC4/TPM3CH4/RSTO pin functions as PTC4 or TPM3CH4.
1 PTC4/TPM3CH4/RSTO pin functions as RSTO.
Freescale Semiconductor
Table 5-5. SBDFR Register Field Descriptions
6 5
COPT STOPE
1 0
1 0
1 0
Figure 5-5. System Options Register 1 (SOPT1)
Table 5-6. SOPT1 Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Chapter 5 Resets, Interrupts, and General System Control
Description
4 3
0 0
RSTOPE
0 0
0 0
0 0
Description
2 1
BKGDPE
1
u 1
0 1
0 1
0
RSTPE
1
u
0
0
101