ROHS MC9S08QE128 Reference Manual page 333

18.3.3.12 Debug FIFO Extended Information Register (DBGFX)
Module Base + 0x000B
7
R PPACC
W
POR
or non- 0
end-run
Reset
U
1
end-run
= Unimplemented or Reserved
Figure 18-13. Debug FIFO Extended Information Register (DBGFX)
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Field
7 PPAGE Access Indicator Bit — This bit indicates whether the captured information in the current FIFO word is
PPACC associated with an extended access through the PPAGE mechanism or not. This is indicated by the internal
signal mmu_ppage_sel which is 1 when the access is through the PPAGE mechanism.
0 The information in the corresponding FIFO word is event-only data or an unpaged 17-bit CPU address with
bit-16 = 0
1 The information in the corresponding FIFO word is a 17-bit flash address with PPAGE[2:0] in the three most
significant bits and CPU address[13:0] in the 14 least significant bits
0 Extended Address Bit 16 — This bit is the most significant bit of the 17-bit core address.
Bit 16
Freescale Semiconductor
6 5
0 0
0 0
0 0
Table 18-14. DBGFX Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
0 0
0 0
0 0
Description
Chapter 18 Debug Module (DBG) (128K)
2 1
0 0
0 0
0 0
0
Bit 16
0
U
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