ROHS MC9S08QE128 Reference Manual page 236

Inter-Integrated Circuit (S08IICV2)
TX
Last Byte
Transmitted
?
N
RXAK=0
?
Y
End of
Y
Addr Cycle
(Master Rx)
?
N
Write Next
Byte to IICD
Switch to
Rx Mode
Generate
Dummy Read
Stop Signal
from IICD
(MST = 0)
NOTES:
1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a
general call address, then the general call must be handled by user software.
2. When 10-bit addressing is used to address a slave, the slave will see an interrupt following the first byte of the extended address. User software must ensure that
for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer
236
RX
Tx/Rx
?
Y
Last
Byte to Be Read
N
?
N
2nd Last
Y
Byte to Be Read
?
N
Generate
Set TXACK =1
Stop Signal
(MST = 0)
Read Data
from IICD
and Store
Figure 12-12. Typical IIC Interrupt Routine
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Clear
IICIF
Master
Y N
Mode
?
Clear ARBL
N
IAAS=1
Y
Y
Y
(Read)
SRW=1
Set TX
Mode
Write Data
to IICD
Set RX
Mode
Dummy Read
from IICD
RTI
Y Arbitration
Lost
?
N
Y
IAAS=1
?
?
N
Data Transfer
Address Transfer
See Note 2
See Note 1
TX/RX
?
?
(Write) TX
N
ACK from
Y
Receiver
?
N
Read Data
Tx Next
from IICD
Byte
and Store
Switch to
Rx Mode
Dummy Read
from IICD
Freescale Semiconductor
RX