ROHS MC9S08QE128 Reference Manual page 73

CBEIE, CCIE and KEYACC bits are readable and writable while all remaining bits read 0 and are not
writable. KEYACC is only writable if KEYEN is set to the enabled state (see
Options Register (FOPT and
Field
5 Enable Security Key Writing
KEYACC 0 Writes to the flash block are interpreted as the start of a command write sequence.
1 Writes to the flash block are interpreted as keys to open the backdoor.
Flash array reads are allowed while KEYACC is set.
4.6.2.4 Flash Protection Register (FPROT and NVPROT)
The FPROT register defines which flash sectors are protected against program or erase operations.
7
R
W
Reset F
FPROT bits are readable and writable as long as the size of the protected flash memory is being increased.
Any write to FPROT that attempts to decrease the size of the protected flash memory will be ignored.
During the reset sequence, the FPROT register is loaded from the flash protection byte, NVPROT. To
change the flash protection that will be loaded during the reset sequence, the flash sector containing
NVPROT must be unprotected and erased, then NVPROT can be reprogrammed.
Trying to alter data in any protected area in the flash memory will result in a protection violation error and
the FPVIOL flag will be set in the FSTAT register. The mass erase of the flash array is not possible if any
of the flash sectors contained in the flash array are protected.
Field
7:1 Flash Protection Size — With FPOPEN set, the FPS bits determine the size of the protected flash address
FPS[6:0] range as shown in
0 Flash Protection Open
FPOPEN 0 Flash array fully protected.
1 Flash array protected address range determined by FPS bits.
Freescale Semiconductor
NVOPT)".
Table 4-16. FCNFG Field Descriptions
6 5
F F
Figure 4-13. Flash Protection Register (FPROT)
Table 4-17. FPROT Field Descriptions
Table 4-18.
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
NOTE
4 3
FPS
F F
Description
Chapter 4 Memory
Section 4.6.2.2, "Flash
2 1
FPOPEN
F F
0
F
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