Low Power Run Mode (Lprun); Modes Of Operation - ROHS MC9S08QE128 Reference Manual

Chapter 3 Modes of Operation
• The bus frequency is 125 kHz or less.
• The ADC if enabled must be configured to use the asynchronous clock source, ADACK, to meet
the ADC minimum frequency requirements. The bandgap channel cannot be converted in low
power run mode.
• The LVDE or LVDSE bit in SPMSC1 register must be clear. LVD and LVW will automatically be
disabled.
• Flash programming/erasing is not allowed.
• ACMP option to compare to internal bandgap reference is not allowed.
• The MCU cannot be in active background mode.
Once these conditions are met, low power run mode can be entered by setting the LPR bit in the SPMSC2
register.
To re-enter standard run mode, simply clear the LPR bit. The LPRS bit in the SPMSC2 register is a
read-only status bit that can be used to determine if the regulator is in full regulation mode or not. When
LPRS is '0', the regulator is in full regulation mode and the MCU can run at full speed in any clock mode.
3.3.1.1 Interrupts in Low Power Run Mode
Low power run mode provides the option to return to full regulation if any interrupt occurs. This is done
by setting the LPWUI bit in the SPMSC2 register. The ICS can then be set for full speed immediately in
the interrupt service routine.
If the LPWUI bit is clear, interrupts will be serviced in low power run mode.
If the LPWUI bit is set, LPR and LPRS bits will be cleared and interrupts will be serviced with the
regulator in full regulation.
3.3.1.2 Resets in Low Power Run Mode
Any reset will exit low power run mode, clear the LPR and LPRS bits and return the device to normal run
mode.
3.3.1.3 BDM in Low Power Run Mode
Low power run mode cannot be entered when the MCU is in active background debug mode.
If a device is in low power run mode, a falling edge on an active BKGD/MS pin exits low power run mode,
clears the LPR and LPRS bits, and returns the device to normal run mode.
3.3.1.4 BDM in Low Power Wait Mode
If a device is in low power wait mode, a falling edge on an active BKGD/MS pin exits low power wait
mode, clears the LPR and LPRS bits, and returns the device to normal run mode.
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MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor