Tpm-Counter Registers (Tpmxcnth:tpmxcntl) - ROHS MC9S08QE128 Reference Manual

16.3.2

TPM-Counter Registers (TPMxCNTH:TPMxCNTL)

The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or
little-endian order which makes this more friendly to various compiler implementations. The coherency
mechanism is automatically restarted by an MCU reset or any write to the timer status/control register
(TPMxSC).
Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the
TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data
involved in the write.
7
R Bit 15
W
Reset 0
Freescale Semiconductor
Table 16-3. TPM-Clock-Source Selection
CLKSB:CLKSA TPM Clock Source to Prescaler Input
00 No clock selected (TPM counter disable)
01
10
11
Table 16-4. Prescale Factor Selection
PS2:PS1:PS0
000
001
010
011
100
101
110
111
6 5
14 13
Any write to TPMxCNTH clears the 16-bit counter
0 0
Figure 16-8. TPM Counter Register High (TPMxCNTH)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Bus rate clock
Fixed system clock
External source
TPM Clock Source Divided-by
1
2
4
8
16
32
64
128
4 3
12 11
0 0
Timer/PWM Module (S08TPMV3)
2 1
10 9
0 0
0
Bit 8
0
293