Iic Data I/O Register (Iicxd) - ROHS MC9S08QE128 Reference Manual

Inter-Integrated Circuit (S08IICV2)
12.3.5

IIC Data I/O Register (IICxD)

7
R
W
Reset 0
Field
7:0 Data — In master transmit mode, when data is written to the IICxD, a data transfer is initiated. The most
DATA significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IICxD register to prevent an inadvertent
initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match has occurred.
Note that the TX bit in IICxC must correctly reflect the desired direction of transfer in master and slave
modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master
receive is desired, then reading the IICxD will not initiate the receive.
Reading the IICxD will return the last byte received while the IIC is configured in either master receive or
slave receive modes. The IICxD does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IICxD correctly by reading it back.
In master transmit mode, the first byte of data written to IICxD following assertion of MST is used for the
address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required
R/W bit (in position bit 0).
226
6 5
0 0
Figure 12-7. IIC Data I/O Register (IICxD)
Table 12-7. IICxD Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
DATA
0 0
Description
NOTE
2 1
0 0
Freescale Semiconductor
0
0