Spi Baud Rate Generation - ROHS MC9S08QE128 Reference Manual

SPE
ENABLE
SPI SYSTEM
SHIFT
OUT
SHIFT
LSBFE
DIRECTION
BUS RATE
SPIBR
CLOCK
CLOCK GENERATOR
MASTER/SLAVE
MSTR
MODE SELECT
15.1.5

SPI Baud Rate Generation

As shown in Figure 15-4, the clock source for the SPI baud rate generator is the bus clock. The three
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
Freescale Semiconductor
Tx BUFFER (WRITE SPIxD)
SPI SHIFT REGISTER
Rx BUFFER (READ SPIxD)
SHIFT Rx BUFFER
Tx BUFFER
CLOCK FULL
CLOCK
LOGIC
MODE FAULT
DETECTION
SPRF
MODF
Figure 15-3. SPI Module Block Diagram
MC9S08QE128 MCU Series Reference Manual, Rev. 2
SHIFT
IN
SPC0
BIDIROE
EMPTY
MASTER CLOCK
SLAVE CLOCK
MODFEN
SSOE
SPTEF
SPTIE
SPIE
Serial Peripheral Interface (S08SPIV3)
PIN CONTROL
M
S
M
S
M
S
MASTER/
SLAVE
SPI
INTERRUPT
REQUEST
MOSI
(MOMI)
MISO
(SISO)
SPSCK
SS
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