ROHS MC9S08QE128 Reference Manual page 334

Chapter 18 Debug Module (DBG) (128K)
18.3.3.13 Debug Control Register (DBGC)
Module Base + 0x000C
7
R
DBGEN
W
POR
or non- 1
end-run
Reset
U
1
end-run
= Unimplemented or Reserved
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the ARM and BRKEN bits are cleared but the remaining
control bits in this register do not change after reset.
Field
7 DBG Module Enable Bit — The DBGEN bit enables the DBG module. The DBGEN bit is forced to zero and
DBGEN cannot be set if the MCU is secure.
0 DBG not enabled
1 DBG enabled
6 Arm Bit — The ARM bit controls whether the debugger is comparing and storing data in FIFO. See
ARM Section 18.4.4.2, "Arming the DBG Module"
0 Debugger not armed
1 Debugger armed
5 Tag or Force Bit — The TAG bit controls whether a debugger or comparator C breakpoint will be requested as
TAG a tag or force breakpoint to the CPU. The TAG bit is not used if BRKEN = 0.
0 Force request selected
1 Tag request selected
4 Break Enable Bit — The BRKEN bit controls whether the debugger will request a breakpoint to the CPU at the
BRKEN end of a trace run, and whether comparator C will request a breakpoint to the CPU.
0 CPU break request not enabled
1 CPU break request enabled
0 Select LOOP1 Capture Mode — This bit selects either normal capture mode or LOOP1 capture mode. LOOP1
LOOP1 is not used in event-only modes.
0 Normal operation - capture COF events into the capture buffer FIFO
1 LOOP1 capture mode enabled. When the conditions are met to store a COF value into the FIFO, compare the
current COF address with the address in comparator C. If these addresses match, override the FIFO capture
and do not increment the FIFO count. If the address does not match comparator C, capture the COF address,
including the PPACC indicator, into the FIFO and into comparator C.
334
6 5
ARM TAG
1 0
0 U
Figure 18-14. Debug Control Register (DBGC)
Table 18-15. DBGC Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
0
BRKEN
0 0
0 0
Description
for more information.
2 1
0 0
LOOP1
0 0
0 0
Freescale Semiconductor
0
0
U