External Signal Description; Register Definition - ROHS MC9S08QE128 Reference Manual

FLL Bypassed Interna
11.1.5.4
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
FLL Bypassed Externa
11.1.5.5
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
FLL Bypassed Externa
11.1.5.6
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
11.1.5.7 Stop (STOP)
In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.
11.2

External Signal Description

There are no ICS signals that connect off chip.
11.3 Register Definition
Figure 11-1 is a summary of ICS registers.
Name
R
ICSC1
W
R
ICSC2
W
R
ICSTRM
W
R
ICSSC
W
Freescale Semiconductor
l Low Power (FBILP)
l (FBE)
l Low Power (FBELP)
Table 11-1. ICS Register Summary
7 6 5
CLKS
BDIV RANGE
DRST
DMX32
DRS
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
RDIV IREFS
HGO LP EREFS
TRIM
IREFST CLKST
Internal Clock Source (S08ICSV3)
2 1
IRCLKEN IREFSTEN
ERCLKEN EREFSTEN
OSCINIT
FTRIM
0
207