Iic Frequency Divider Register (Iicxf) - ROHS MC9S08QE128 Reference Manual

Inter-Integrated Circuit (S08IICV2)
12.3.2

IIC Frequency Divider Register (IICxF)

7
R
MULT
W
Reset 0
Field
7:6 IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL
MULT divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
5:0 IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT
ICR bits are used to determine the IIC baud rate, the SDA hold time, the SCL Start hold time and the SCL Stop hold
time. Table 12-4
The SCL divider multiplied by multiplier factor mul is used to generate IIC baud rate.
SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data).
SCL Start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the
falling edge of SCL (IIC clock).
SCL Start hold time = bus period (s) * mul * SCL Start hold value
SCL Stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA
SDA (IIC data) while SCL is high (Stop condition).
For example if the bus speed is 8MHz, the table below shows the possible hold time values with different
ICR and MULT selections to achieve an IIC baud rate of 100kbps.
MULT
0x2
0x1
0x1
0x0
0x0
222
6 5
0 0
Figure 12-4. IIC Frequency Divider Register (IICxF)
Table 12-3. IICxF Field Descriptions
provides the SCL divider and hold values for corresponding values of the ICR.
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
SDA hold time = bus period (s) * mul * SDA hold value
SCL Stop hold time = bus period (s) * mul * SCL Stop hold value
ICR
0x00
0x07
0x0B
0x14
0x18
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
ICR
0 0
Description
Hold times (μs)
SDA SCL Start
3.500 4.750
2.500 4.250
2.250 4.000
2.125 4.000
1.125 3.000
2 1
0 0
Eqn. 12-1
Eqn. 12-2
Eqn. 12-3
Eqn. 12-4
SCL Stop
5.125
5.125
5.250
5.250
5.500
Freescale Semiconductor
0
0