Port G Registers - ROHS MC9S08QE128 Reference Manual

Field
7:0 Internal Pull Enable for Port F Bits — Each of these control bits determines if the internal pull-up device is
PTFPE[7:0] enabled for the associated PTF pin. For port F pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port F bit n.
1 Internal pull-up device enabled for port F bit n.
6.5.6.4 Port F Slew Rate Enable Register (PTFSE)
7
R
PTFSE7
W
Reset: 0
Field
7:0 Output Slew Rate Enable for Port F Bits — Each of these control bits determines if the output slew rate control
PTFSE[7:0] is enabled for the associated PTF pin. For port F pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port F bit n.
1 Output slew rate control enabled for port F bit n.
6.5.6.5 Port F Drive Strength Selection Register (PTFDS)
7
R
PTFDS7
W
Reset: 0
Figure 6-38. Drive Strength Selection for Port F Register (PTFDS)
Field
7:0 Output Drive Strength Selection for Port F Bits — Each of these control bits selects between low and high
PTFDS[7:0] output drive for the associated PTF pin. For port F pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port F bit n.
1 High output drive strength selected for port F bit n.
6.5.7

Port G Registers

Port G is controlled by the registers listed below.
Freescale Semiconductor
Table 6-34. PTFPE Register Field Descriptions
6 5
PTFSE6 PTFSE5
0 0
Figure 6-37. Slew Rate Enable for Port F Register (PTFSE)
Table 6-35. PTFSE Register Field Descriptions
6 5
PTFDS6 PTFDS5
0 0
Table 6-36. PTFDS Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
PTFSE4 PTFSE3
0 0
Description
4 3
PTFDS4 PTFDS3
0 0
Description
Chapter 6 Parallel Input/Output Control
2 1
PTFSE2 PTFSE1
0 0
2 1
PTFDS2 PTFDS1
0 0
0
PTFSE0
0
0
PTFDS0
0
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