RoHS MC9S08QE96 Manuals

Manuals and User Guides for RoHS MC9S08QE96. We have 1 RoHS MC9S08QE96 manual available for free PDF download: Reference Manual

RoHS MC9S08QE96 Reference Manual (345 pages)

Brand: RoHS | Category: Microcontrollers | Size: 1.72 MB

Table of Contents
8
Section Number Title Page

9
- Devices in the MC9S08QE128 Series
  18
Chapter 1 Device Overview

19
- MCU Block Diagram
  20
- System Clock Distribution
  23
- Pins and Connections
  24
- Device Pin Assignment
  24
Chapter 2 Pins and Connections

25
- Recommended System Connections
  31
  - Power
    32
  - Oscillator
    32
  - RESET and RSTO
    33
  - Background / Mode Select (BKGD/MS)
    33
  - General-Purpose I/O and Peripheral Ports
    34
- Refh Refl
  34
  - ADC Reference Pins
    35
- Modes of Operation 3.1 Introduction
  38
- Features
  38
- Run Mode
  38
  - Low Power Run Mode (Lprun)
    39
Chapter 3 Modes of Operation

39
- Active Background Mode
  41
- Wait Mode
  41
  - Low Power Wait Mode (Lpwait)
    42
- Stop Modes
  42
  - Stop2 Mode
    42
  - Stop3 Mode
    44
- Mode Selection
  44
- MC9S08QE128 Series Memory Map
  51
Chapter 4 Memory

51
- Reset and Interrupt Vector Assignments
  53
- Register Addresses and Bit Assignments
  55
- Memory Management Unit
  63
  - Features
    63
  - Register Deﬁnition
    63
  - Functional Description
    66
- Ram
  69
- Flash
  69
  - Features
    70
  - Register Descriptions
    70
  - Functional Description
    77
  - Operating Modes
    86
  - Flash Module Security
    86
  - Resets
    88
- Introduction
  89
- Features
  89
- MCU Reset
  89
- Computer Operating Properly (COP) Watchdog
  90
- Interrupts
  91
Chapter 5

92
Chapter 6 Parallel Input/Output Control

111
- Port Data and Data Direction
  111
- Pull-Up, Slew Rate, and Drive Strength
  112
  - Port Internal Pull-Up Enable
    112
  - Port Slew Rate Enable
    112
  - Port Drive Strength Select
    112
- Port Data Set, Clear and Toggle Data Registers
  113
  - Port Data Set Registers
    114
  - Port Data Clear Registers
    114
  - Port Data Toggle Register
    114
- Pin Behavior in Stop Modes
  114
- Parallel I/O and Pin Control Registers
  114
  - Port a Registers
    115
  - Port B Registers
    117
  - Port C Registers
    119
  - Port D Registers
    123
  - Port E Registers
    125
  - Port F Registers
    129
  - Port G Registers
    131
  - Port H Registers
    133
  - Port J Registers
    135
Chapter 7 Keyboard Interrupt (S08KBIV2)

139
- Introduction
  139
  - KBI Clock Gating
    139
  - Features
    139
  - Modes of Operation
    139
  - Block Diagram
    140
- External Signal Description
  140
- Register Deﬁnition
  141
- Functional Description
  142
  - Edge Only Sensitivity
    143
  - Edge and Level Sensitivity
    143
  - Pull-Up/Pull-Down Resistors
    143
  - Keyboard Interrupt Initialization
    143
Chapter 8 Central Processor Unit (S08CPUV4)

145
- Introduction
  145
  - Features
    145
- Programmer's Model and CPU Registers
  146
  - Accumulator (A)
    146
  - Index Register (H:X)
    146
  - Stack Pointer (SP)
    147
  - Program Counter (PC)
    147
  - Condition Code Register (CCR)
    147
- Addressing Modes
  149
  - Inherent Addressing Mode (INH)
    149
  - Relative Addressing Mode (REL)
    149
  - Immediate Addressing Mode (IMM)
    149
  - Direct Addressing Mode (DIR)
    150
  - Extended Addressing Mode (EXT)
    150
  - Indexed Addressing Mode
    150
- Special Operations
  151
  - Reset Sequence
    151
  - Interrupt Sequence
    151
  - Wait Mode Operation
    152
  - Stop Mode Operation
    152
  - BGND Instruction
    153
- HCS08 Instruction Set Summary
  155
Chapter 9 Analog Comparator 3V (ACMPVLPV1)

167
- Introduction
  167
  - ACMP Conﬁguration Information
    167
  - ACMP/TPM Conﬁguration Information
    167
  - ACMP Clock Gating
    167
  - Interrupt Vectors
    168
  - Features
    170
  - Modes of Operation
    170
  - Block Diagram
    170
- External Signal Description
  171
- Register Deﬁnition
  171
  - Acmpx Status and Control Register (Acmpxsc)
    172
- Functional Description
  173
Chapter 10 Analog-To-Digital Converter (S08ADC12V1)

175
- Introduction
  175
  - ADC Clock Gating
    175
  - Module Conﬁgurations
    177
  - Features
    179
  - Block Diagram
    179
- External Signal Description
  180
  - Analog Power
    181
    
    Ddad )
    181
  - Analog Ground
    181
    
    Ssad )
    181
    
    Refh )
    181
  - Voltage Reference Low
    181
    
    Refl )
    181
  - Analog Channel Inputs (Adx)
    181
- Register Deﬁnition
  181
- Functional Description
  190
  - Clock Select and Divide Control
    190
  - Input Select and Pin Control
    191
  - Hardware Trigger
    191
  - Conversion Control
    191
  - Automatic Compare Function
    194
  - MCU Wait Mode Operation
    194
  - MCU Stop3 Mode Operation
    194
  - MCU Stop1 and Stop2 Mode Operation
    195
- Initialization Information
  195
  - ADC Module Initialization Example
    195
- Application Information
  197
  - External Pins and Routing
    197
  - Sources of Error
    199
Chapter 11 Internal Clock Source (S08ICSV3)

203
- Introduction
  203
  - External Oscillator
    203
  - Stop2 Mode Considerations
    203
  - Features
    205
  - Block Diagram
    205
  - Modes of Operation
    206
- External Signal Description
  207
- Register Deﬁnition
  207
  - ICS Control Register 1 (ICSC1)
    208
  - ICS Control Register 2 (ICSC2)
    209
  - ICS Trim Register (ICSTRM)
    209
  - ICS Status and Control (ICSSC)
    210
- Functional Description
  212
  - Operational Modes
    212
  - Mode Switching
    214
  - Bus Frequency Divider
    215
  - Low Power Bit Usage
    215
  - DCO Maximum Frequency with 32.768 Khz Oscillator
    215
  - Internal Reference Clock
    215
  - External Reference Clock
    216
  - Fixed Frequency Clock
    216
  - Local Clock
    216
Chapter 12 Inter-Integrated Circuit (S08IICV2)

217
- Introduction
  217
  - Module Conﬁguration
    217
  - Interrupt Vectors
    217
  - Features
    219
  - Modes of Operation
    219
  - Block Diagram
    220
- External Signal Description
  220
  - SCL - Serial Clock Line
    220
  - SDA - Serial Data Line
    220
- Register Deﬁnition
  221
  - IIC Address Register (Iicxa)
    221
  - IIC Frequency Divider Register (Iicxf)
    222
  - IIC Control Register (Iicxc1)
    224
  - IIC Status Register (Iicxs)
    225
  - IIC Data I/O Register (IICXD)
    226
  - IIC Control Register 2 (Iicxc2)
    227
- Functional Description
  228
  - IIC Protocol
    228
  - 10-Bit Address
    232
  - General Call Address
    233
- Resets
  233
- Interrupts
  233
  - Byte Transfer Interrupt
    233
  - Address Detect Interrupt
    233
  - Arbitration Lost Interrupt
    233
- Initialization/Application Information
  235
Chapter 13 Real-Time Counter (S08RTCV1)

237
- Introduction
  237
  - ADC Hardware Trigger
    237
  - RTC Clock Sources
    237
  - RTC Modes of Operation
    237
  - RTC Clock Gating
    237
  - Interrupt Vector
    238
  - Features
    240
  - Modes of Operation
    240
  - Block Diagram
    241
- External Signal Description
  241
- Register Deﬁnition
  241
- Functional Description
  244
  - RTC Operation Example
    245
- Initialization/Application Information
  245
Chapter 14 Serial Communications Interface (S08SCIV4)

247
- Introduction
  247
  - SCI Clock Gating
    247
  - Interrupt Vectors
    247
  - Features
    250
  - Modes of Operation
    250
  - Block Diagram
    251
- Register Deﬁnition
  253
  - SCI Baud Rate Registers (Scixbdh, Scixbdl)
    253
  - SCI Control Register 1 (Scixc1)
    254
  - SCI Control Register 2 (Scixc2)
    255
  - SCI Status Register 1 (Scixs1)
    256
  - SCI Status Register 2 (Scixs2)
    258
  - SCI Control Register 3 (Scixc3)
    259
  - SCI Data Register (Scixd)
    260
- Functional Description
  260
  - Baud Rate Generation
    260
  - Transmitter Functional Description
    261
  - Receiver Functional Description
    262
  - Interrupts and Status Flags
    264
  - Additional SCI Functions
    265
Chapter 15 Serial Peripheral Interface (S08SPIV3)

267
- Introduction
  267
  - SPI Clock Gating
    267
  - Interrupt Vector
    267
  - Features
    269
  - Block Diagrams
    269
  - SPI Baud Rate Generation
    271
- External Signal Description
  272
  - SPSCK - SPI Serial Clock
    272
  - MOSI - Master Data Out, Slave Data in
    272
  - MISO - Master Data In, Slave Data out
    272
  - SS - Slave Select
    272
- Modes of Operation
  273
  - SPI in Stop Modes
    273
- Register Deﬁnition
  273
  - SPI Control Register 1 (Spixc1)
    273
  - SPI Control Register 2 (Spixc2)
    274
  - SPI Baud Rate Register (Spixbr)
    275
  - SPI Status Register (Spixs)
    276
  - SPI Data Register (Spixd)
    277
- Functional Description
  278
  - SPI Clock Formats
    278
  - SPI Interrupts
    281
  - Mode Fault Detection
    281
Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3)

283
- Introduction
  283
  - ACMP/TPM Conﬁguration Information
    283
  - TPM Clock Gating
    283
  - Interrupt Vector
    283
  - Features
    285
  - Modes of Operation
    285
  - Block Diagram
    286
- Signal Description
  288
  - Detailed Signal Descriptions
    288
- Register Deﬁnition
  292
- Functional Description
  298
  - Counter
    298
  - Channel Mode Selection
    300
- Reset Overview
  303
  - General
    303
  - Description of Reset Operation
    303
- Interrupts
  303
  - Description of Interrupt Operation
    304
Chapter 17 Development Support

307
- Introduction
  307
  - Forcing Active Background
    307
  - DBG Clock Gating
    307
  - Module Conﬁguration
    307
  - Features
    308
- Background Debug Controller (BDC)
  308
  - BKGD Pin Description
    309
  - Communication Details
    309
  - BDC Commands
    313
  - BDC Hardware Breakpoint
    315
- Register Deﬁnition
  315
  - BDC Registers and Control Bits
    316
  - System Background Debug Force Reset Register (SBDFR)
    318
Chapter 18 Debug Module (DBG) (128K)

321
- Introduction
  321
  - Features
    321
  - Modes of Operation
    322
  - Block Diagram
    322
- Signal Description
  322
- Memory Map and Registers
  323
  - Module Memory Map
    323
  - Register Descriptions
    325
- Functional Description
  338
  - Comparator
    338
  - Breakpoints
    339
  - Trigger Selection
    339
  - Trigger Break Control (TBC)
    340
  - Fifo
    343
  - Interrupt Priority
    344
- Resets
  344
- Interrupts
  345
- Electrical Speciﬁcations
  345

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RoHS MC9S08QE96 Manuals

RoHS MC9S08QE96 Reference Manual (345 pages)

Table of Contents

Section Number Title Page

Chapter 1 Device Overview

Chapter 2 Pins and Connections

Chapter 3 Modes of Operation

Chapter 4 Memory

Chapter 5

Chapter 6 Parallel Input/Output Control

Chapter 7 Keyboard Interrupt (S08KBIV2)

Chapter 8 Central Processor Unit (S08CPUV4)

Chapter 9 Analog Comparator 3V (ACMPVLPV1)

Chapter 10 Analog-To-Digital Converter (S08ADC12V1)

Chapter 11 Internal Clock Source (S08ICSV3)

Chapter 12 Inter-Integrated Circuit (S08IICV2)

Chapter 13 Real-Time Counter (S08RTCV1)

Chapter 14 Serial Communications Interface (S08SCIV4)

Chapter 15 Serial Peripheral Interface (S08SPIV3)

Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3)

Chapter 17 Development Support

Chapter 18 Debug Module (DBG) (128K)

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