Inter-Integrated Circuit (S08Iicv2); Introduction; Module Configuration; Interrupt Vectors - ROHS MC9S08QE128 Reference Manual

Chapter 12

Inter-Integrated Circuit (S08IICV2)

12.1

Introduction

The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The
interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of bus clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
All MC9S08QE128 Series MCUs feature the one or two IICs, as shown in
The SDA and SCL should not be driven above V
open-drain containing a protection diode to V
12.1.1 Module Configuration
The IIC1 module pins, SDA and SCL can be repositioned under software control using SOPT2[IIC1PS]
as shown in Table 12-1. This bit selects which general-purpose I/O ports are associated with IIC1
operation.
12.1.2

Interrupt Vectors

For MC9S08QE128 Series MCUs with two IICs, both IICs share a single interrupt vector. When interrupts
are enabled for both IICs, the IICF bit must be polled in the IIC1S and IIC2S registers to determine which
IIC caused the interrupt. See
vector assignment.
Freescale Semiconductor
Table 12-1. IIC1 Position Options
SOPT2[IIC1PS] Port Pin for SDA
0 (default)
1
Section 4.2, "Reset and Interrupt Vector
MC9S08QE128 MCU Series Reference Manual, Rev. 2
I2C
NOTE
. These pins are psuedo
DD
.
DD
Port Pin for SCL
PTA2
PTB6
Assignments," for the IIC interrupt
Figure 12-1.
PTA3
PTB7
217