Memory Map And Registers; Module Memory Map - ROHS MC9S08QE128 Reference Manual

18.3

Memory Map and Registers

This section provides a detailed description of all DBG registers accessible to the end user.
18.3.1

Module Memory Map

Table 18-1 shows the registers contained in the DBG module.
Address
Base + $0000
Base + $0001
Base + $0002
Base + $0003
Base + $0004
Base + $0005
Base + $0006
Base + $0007
Base + $0008
Base + $0009
Base + $000A
Base + $000B
Base + $000C
Base + $000D
Base + $000E
Base + $000F
Freescale Semiconductor
Table 18-1. Module Memory Map
Debug Comparator A High Register (DBGCAH)
Debug Comparator A Low Register (DBGCAL)
Debug Comparator B High Register (DBGCBH)
Debug Comparator B Low Register (DBGCBL)
Debug Comparator C High Register (DBGCCH)
Debug Comparator C Low Register (DBGCCL)
Debug FIFO High Register (DBGFH)
Debug FIFO Low Register (DBGFL)
Debug Comparator A Extension Register (DBGCAX)
Debug Comparator B Extension Register (DBGCBX)
Debug Comparator C Extension Register (DBGCCX)
Debug FIFO Extended Information Register (DBGFX)
Debug Control Register (DBGC)
Debug Trigger Register (DBGT)
Debug Status Register (DBGS)
Debug FIFO Count Register (DBGCNT)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Chapter 18 Debug Module (DBG) (128K)
Use Access
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read only
Read only
Read/write
Read/write
Read/write
Read only
Read/write
Read/write
Read only
Read only
323