Port H Registers - ROHS MC9S08QE128 Reference Manual

Field
7:0 Internal Pull Enable for Port G Bits — Each of these control bits determines if the internal pull-up device is
PTGPE[7:0] enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port G bit n.
1 Internal pull-up device enabled for port G bit n.
6.5.7.4 Port G Slew Rate Enable Register (PTGSE)
7
R
PTGSE7
W
Reset: 0
Field
7:0 Output Slew Rate Enable for Port G Bits — Each of these control bits determines if the output slew rate control
PTGSE[7:0] is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
6.5.7.5 Port G Drive Strength Selection Register (PTGDS)
7
R
PTGDS7
W
Reset: 0
Figure 6-43. Drive Strength Selection for Port G Register (PTGDS)
Field
7:0 Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high
PTGDS[7:0] output drive for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port G bit n.
1 High output drive strength selected for port G bit n.
6.5.8

Port H Registers

Port H is controlled by the registers listed below.
Freescale Semiconductor
Table 6-39. PTGPE Register Field Descriptions
6 5
PTGSE6 PTGSE5
0 0
Figure 6-42. Slew Rate Enable for Port G Register (PTGSE)
Table 6-40. PTGSE Register Field Descriptions
6 5
PTGDS6 PTGDS5
0 0
Table 6-41. PTGDS Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
PTGSE4 PTGSE3
0 0
Description
4 3
PTGDS4 PTGDS3
0 0
Description
Chapter 6 Parallel Input/Output Control
2 1
PTGSE2 PTGSE1
0 0
2 1
PTGDS2 PTGDS1
0 0
0
PTGSE0
0
0
PTGDS0
0
133