ROHS MC9S08QE128 Reference Manual page 163

Source
Operation
Form
SUB #opr8i
SUB opr8a
SUB opr16a
SUB oprx16,X
Subtract
SUB oprx8,X
SUB ,X
SUB oprx16,SP
SUB oprx8,SP
SWI Software Interrupt
Transfer Accumulator to
TAP
CCR
Transfer Accumulator to
TAX
X (Index Register Low)
Transfer CCR to
TPA
Accumulator
TST opr8a
TSTA
TSTX
Test for Negative or Zero
TST oprx8,X
TST ,X
TST oprx8,SP
TSX Transfer SP to Index Reg.
Transfer X (Index Reg.
TXA
Low) to Accumulator
TXS Transfer Index Reg. to SP
Enable Interrupts; Wait
WAIT
for Interrupt
1
Bus clock frequency is one-half of the CPU clock frequency.
Freescale Semiconductor
Table 8-2. HCS08 Instruction Set Summary (Sheet 7 of 7)
PC ← (PC) + 0x0001
Push (PCL); SP ← (SP) – 0x0001
Push (PCH); SP ← (SP) – 0x0001
Push (X); SP ← (SP) – 0x0001
Push (A); SP ← (SP) – 0x0001
Push (CCR); SP ← (SP) – 0x0001
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
(P
SW)
H:X ← (SP) + 0x0001
SP ← (H:X) – 0x0001
I bit ← 0; Halt CPU
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
V H I N Z C
A ← (A) – (M)
– – 1 – – –
I ← 1;
CCR ← (A)
X ← (A)
– – – – – –
A ← (CCR)
– – – – – –
(M) – 0x00
(A) – 0x00
(X) – 0x00
0 – –
(M) – 0x00
(M) – 0x00
(M) – 0x00
– – – – – –
A ← (X)
– – – – – –
– – – – – –
– – 0 – – –
Chapter 8 Central Processor Unit (S08CPUV4)
Effect
on CCR
IMM
DIR
EXT
IX2
– –
IX1
IX
SP2 9ED0
SP1 9EE0
INH
INH
INH
INH
DIR
INH
INH
–
IX1
IX
SP1 9E6D
INH
INH
INH
INH
A0 ii 2
B0 dd 3
C0 hh ll 4
D0 ee ff 4
E0 ff 3
F0 3
ee ff 5
ff 4
83 11
84 1
97 1
85 1
3D dd 4
4D 1
5D 1
6D ff 4
7D 3
ff 5
95 2
9F 1
94 2
8F 2+
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