Spi Status Register (Spixs) - ROHS MC9S08QE128 Reference Manual

Serial Peripheral Interface (S08SPIV3)
15.4.4

SPI Status Register (SPIxS)

This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Writes have no meaning or effect.
7
R SPRF
W
Reset 0
= Unimplemented or Reserved
276
Table 15-5. SPI Baud Rate Prescaler Divisor
SPPR2:SPPR1:SPPR0
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Table 15-6. SPI Baud Rate Divisor
SPR2:SPR1:SPR0
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
6 5
0 SPTEF
0 1
Figure 15-8. SPI Status Register (SPIxS)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Prescaler Divisor
1
2
3
4
5
6
7
8
Rate Divisor
2
4
8
16
32
64
128
256
4 3
MODF 0
0 0
2 1
0 0
0 0
Freescale Semiconductor
0
0
0