Functional Description - ROHS MC9S08QE128 Reference Manual

4.6.3

Functional Description

4.6.3.1 Flash Command Operations
Flash command operations are used to execute program, erase, and erase verify algorithms described in
this section. The program and erase algorithms are controlled by the flash memory controller whose time
base, FCLK, is derived from the bus clock via a programmable divider.
The next sections describe:
1. How to write the FCDIV register to set FCLK
2. Command write sequences to program, erase, and erase verify operations on the flash memory
3. Valid flash commands
4. Effects resulting from illegal flash command write sequences or aborting flash operations
4.6.3.1.1 Writing the FCDIV Register
Prior to issuing any flash command after a reset, the user is required to write the FCDIV register to divide
the bus clock down to within the 150 kHz to 200 kHz range. This register can be written only once, so
normally this write is done during reset initialization. FCDIV cannot be written if the access error flag,
FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV
register. One period of the resulting clock (1/f
and erase pulses. An integer number of these timing pulses are used by the command processor to complete
a program or erase command.
Table 4-22 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (f ). The time for one cycle of FCLK is t
FCLK
of cycles of FCLK and as an absolute time for the case where t
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Parameter
Byte program
Byte program (burst)
Page erase
Mass erase
1
Excluding start/end overhead
Program and erase command execution time will increase proportionally
with the period of FCLK. Programming or erasing the flash memory with
FCLK < 150 kHz should be avoided. Setting FCDIV to a value such that
FCLK < 150 kHz can destroy the flash memory due to overstress. Setting
FCDIV to a value such that FCLK > 200 kHz can result in incomplete
programming or erasure of the flash memory cells.
Freescale Semiconductor
) is used by the command processor to time program
FCLK
Table 4-22. Program and Erase Times
Cycles of FCLK
4000
20,000
NOTE
MC9S08QE128 MCU Series Reference Manual, Rev. 2
= 1/f . The times are shown as a number
FCLK FCLK
= 5 μs. Program and erase times
FCLK
Time if FCLK = 200 kHz
9
4
Chapter 4 Memory
45 μs
20 μs 1
20 ms
100 ms
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