ROHS MC9S08QE128 Reference Manual page 234

Inter-Integrated Circuit (S08IICV2)
• SDA sampled as a low when the master drives a high during an address or data transmit cycle.
• SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
• A START cycle is attempted when the bus is busy.
• A repeated START cycle is requested in slave mode.
• A STOP condition is detected when the master did not request it.
This bit must be cleared by software by writing a 1 to it.
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MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor