Functional Description - ROHS MC9S08QE128 Reference Manual

Chapter 4 Memory
4.4.2.5 Linear Byte Register (LB)
This register is one of three data registers that the user can use to access any flash memory location in the
extended address map. When LB is accessed the contents of LAP2:LAP0 make up the extended address
of the flash memory location to be addressed.
7
R
D7
W
Reset: 0
Field
7:0 Reads of this register returns the data value pointed to by the linear address pointer, LAP2:LAP0. Writes to this
D7:D0 register will write the data value to the memory location specified by the linear address pointer. Writes to this
register are most commonly used when writing to the flash block(s) during programming.
4.4.2.6 Linear Address Pointer Add Byte Register (LAPAB)
The user can increase or decrease the contents of LAP2:LAP0 by writing a 2s compliment value to
LAPAB. The value written will be added to the current contents of LAP2:LAP0.
7
R 0
W D7
Reset: 0
Figure 4-9. Linear Address Pointer Add Byte Register (LAPAB)
Table 4-10. Linear Address Pointer Add Byte Register Field Descriptions
Field
7:0 The 2s compliment value written to LAPAB will be added to contents of the linear address pointer register,
D7:D0 LAP2:LAP0. Writing a value of 0x7f to LAPAB will increase LAP by 127, a value of 0xff will decrease LAP by 1,
and a value of 0x80 will decrease LAP by 128.
4.4.3

Functional Description

4.4.3.1 Memory Expansion
The HCS08 Core architecture limits the CPU addressable space available to 64K bytes. The Program Page
(PPAGE) allows for integrating up to 4M byte of flash into the system by selecting one of the 16K byte
blocks to be accessed through the paging window located at 0x8000-0xBFFF. The MMU module also
provides a linear address pointer that allows extension of data access up to 4M bytes.
66
6 5
D6 D5
0 0
Figure 4-8. Linear Byte Register (LB)
Table 4-9. Linear Data Register Field Descriptions
6 5
0 0
D6 D5
0 0
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
D4 D3 D2
0 0
Description
4 3
0 0
D4 D3 D2
0 0
Description
2 1 0
D1 D0
0 0 0
2 1 0
0 0 0
D1 D0
0 0 0
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