ROHS MC9S08QE128 Reference Manual page 126

Chapter 6 Parallel Input/Output Control
6.5.5.1 Port E Data Register (PTED)
7
R
PTED7
W
Reset: 0
Field
7:0 Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
PTED[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
6.5.5.2 Port E Data Direction Register (PTEDD)
7
R
PTEDD7
W
Reset: 0
Field
7:0 Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTEDD[7:0] PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
6.5.5.3 Port E Data Set Register (PTESET)
7
R
W PTESET7 PTESET6
Reset: 0
126
6 5
PTED6 PTED5
0 0
Figure 6-26. Port E Data Register (PTED)
Table 6-24. PTED Register Field Descriptions
6 5
PTEDD6 PTEDD5
0 0
Figure 6-27. Port E Data Direction Register (PTEDD)
Table 6-25. PTEDD Register Field Descriptions
6 5
PTESET5
0 0
Figure 6-28. Port E Data Set Register (PTESET)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
PTED4 PTED3
0 0
Description
4 3
PTEDD4 PTEDD3
0 0
Description
4 3
PTESET4 PTESET3
0 0
2 1
PTED2 PTED1
0 0
2 1
PTEDD2 PTEDD1
0 0
2 1
PTESET2 PTESET1
0 0
Freescale Semiconductor
0
PTED0
0
0
PTEDD0
0
0
PTESET0
0