Serial Communications Interface (S08Sciv4); Introduction; Sci Clock Gating; Interrupt Vectors - ROHS MC9S08QE128 Reference Manual

Chapter 14

Serial Communications Interface (S08SCIV4)

14.1

Introduction

Figure 14-1 shows the MC9S08QE128 Series block diagram with the SCI highlighted.
Ignore any references to stop1 low-power mode in this chapter, because the
MC9S08QE128 device does not support it.
14.1.1

SCI Clock Gating

The bus clock to SCI1 and SCI2 can be gated on and off using the SCGC1[SCI1,SCI2] bits, respectively.
These bits are set after any reset, which enables the bus clock to these modules. To conserve power, these
bits can be cleared to disable the clock to either of these modules when not in use. See
"Peripheral Clock Gating," for details.
14.1.2

Interrupt Vectors

Each SCI module contains three interrupt sources: transmit, receive, and error. See
Interrupt Vector Assignments," for a list of the SCI interrupt vector assignments.
Freescale Semiconductor
NOTE
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Section 5.7,
Section 4.2, "Reset and
247