System Power Management Status And Control 2 Register (Spmsc2) - ROHS MC9S08QE128 Reference Manual

Field
2 Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
LVDE of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
0 Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the
BGBE ADC module on one of its internal channels or as a voltage reference for ACMP module.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
5.8.8 System Power Management Status and Control 2 Register
(SPMSC2)
This high page register contains status and control bits to configure the low power run and wait modes as
well as configure the stop mode behavior of the MCU. See
(LPRun)," Section 3.5.1, "Low Power Wait Mode
information.
7
R
LPR
W
Reset: 0
Stop2
0
Wakeup:
= Unimplemented or Reserved
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
1
PPDE is a write-once bit that can be used to disable the PPDC bit until any reset.
Field
7 Low Power Regulator Control — The LPR bit controls entry into the low power run and wait modes in which
LPR the voltage regulator is put into standby. This bit cannot be set if PPDC=1. If PPDC and LPR are set in a single
write instruction, only PPDC will actually be set. Automatically cleared when LPWUI is set and an interrupt
occurs.
0 Low-power run and low-power wait modes are disabled.
1 Low-power run and low-power wait modes are enabled.
6 Low Power Regulator Status — This read-only status bit indicates that the voltage regulator has entered into
LPRS standby for the low power run or wait mode.
0 The voltage regulator is not currently in standby.
1 The voltage regulator is currently in standby.
5 Low Power Wake Up on Interrupt — This bit controls whether or not the voltage regulator exits standby when
LPWUI any active MCU interrupt occurs.
0 The voltage regulator will remain in standby on an interrupt.
1 The voltage regulator will exit standby on an interrupt.
Freescale Semiconductor
Table 5-10. SPMSC1 Register Field Descriptions (continued)
6 5
LPRS
LPWUI
0 0
0 u
Table 5-11. SPMSC2 Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Chapter 5 Resets, Interrupts, and General System Control
Description
Section 3.3.1, "Low Power Run Mode
(LPWait)," and Section 3.6, "Stop
4 3
0 PPDF
PPDACK
0 0
0 1
u = Unaffected by reset
Description
Modes," for more
2 1
0
1
PPDE
0 0
0 1
0
PPDC
0
1
105