ROHS MC9S08QE128 Reference Manual page 326

Chapter 18 Debug Module (DBG) (128K)
Field
Bits 7–0 Comparator A Low Compare Bits — The Comparator A Low compare bits control whether Comparator A will
compare the address bus bits [7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
18.3.3.3 Debug Comparator B High Register (DBGCBH)
Module Base + 0x0002
7
R
Bit 15
W
POR
or non- 0
end-run
Reset
U
1
end-run
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Field
Bits 15–8 Comparator B High Compare Bits — The Comparator B High compare bits control whether Comparator B will
compare the address bus bits [15:8] to a logic 1 or logic 0. Not used in Full mode.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
18.3.3.4 Debug Comparator B Low Register (DBGCBL)
Module Base + 0x0003
7
R
Bit 7
W
POR
or non- 0
end-run
Reset
U
1
end-run
326
Table 18-4. DBGCAL Field Descriptions
6 5
Bit 14 Bit 13
0 0
U U
Figure 18-4. Debug Comparator B High Register (DBGCBH)
Table 18-5. DBGCBH Field Descriptions
6 5
Bit 6 Bit 5
0 0
U U
Figure 18-5. Debug Comparator B Low Register (DBGCBL)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
Bit 12 Bit 11
0 0
U U
Description
4 3
Bit 4 Bit 3
0 0
U U
2 1
Bit 10 Bit 9
0 0
U U
2 1
Bit 2 Bit 1
0 0
U U
Freescale Semiconductor
0
Bit 8
0
U
0
Bit 0
0
U