Register Definition; Kbi Interrupt Status And Control Register (Kbixsc) - ROHS MC9S08QE128 Reference Manual

7.3 Register Definition
The KBI includes three registers:
• An 8-bit pin status and control register.
• An 8-bit pin enable register.
• An 8-bit edge select register.
Refer to the direct-page register summary in the
all KBI registers. This section refers to registers and control bits only by their names and relative address
offsets.
Some MCUs may have more than one KBI, so register names include placeholder characters to identify
which KBI is being referenced.
7.3.1

KBI Interrupt Status and Control Register (KBIxSC)

7
R 0
W
Reset: 0
Figure 7-2. KBI Interrupt Status and Control Register (KBIxSC)
Field
3 KBI Interrupt Flag — KBF indicates when a KBI interrupt is detected. Writes have no effect on KBF.
KBF 0 No KBI interrupt detected.
1 KBI interrupt detected.
2 KBI Interrupt Acknowledge — Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always
KBACK reads as 0.
1 KBI Interrupt Enable — KBIE determines whether a KBI interrupt is requested.
KBIE 0 KBI interrupt request not enabled.
1 KBI interrupt request enabled.
0 KBI Detection Mode — KBIMOD (along with the KBIES bits) controls the detection mode of the KBI interrupt
KBIMOD pins.
0 KBI pins detect edges only.
1 KBI pins detect both edges and levels.
Freescale Semiconductor
Memory
6 5
0 0
0 0
Table 7-3. KBIxSC Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
chapter for the absolute address assignments for
4 3
0 KBF
KBACK
0 0
Description
Chapter 7 Keyboard Interrupt (S08KBIV2)
2 1
0
KBIE
0 0
0
KBIMOD
0
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