Low Power Wait Mode (Lpwait); Stop Modes; Stop2 Mode - ROHS MC9S08QE128 Reference Manual

If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter either of
the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate
bits in the Section 5.8.10, "System Clock Gating Control 1 Register
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Register SOPT1 BDCSCR
Bit
STOPE ENBDM
name
0
1
1
1
1
1
ENBDM is located in the BDCSCR, which is only accessible through BDC commands; see the "BDC Status and Control
Register (BDCSCR)" section in
2
When in Stop3 mode with BDM enabled, The S
3.6.1

Stop2 Mode

3.6.1.1 Stop2 Entry
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in
3.6.1.2 Behavior in Stop2
Most of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM and
optionally the RTC and low power oscillator (LPO), and the low-range low-gain oscillator (XOSCVLP).
Upon entering stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.
3.6.1.3 Exit from Stop2
Exit from stop2 is performed by asserting the wake-up pin (PTA5/IRQ/TCLK/RESET) on the MCU.
PTA5/IRQ/TPM1CLK/RESET functions as an active-low wakeup input
when the MCU is in stop2. The pullup on this pin is not automatically
enabled in stop2. To enable the internal pullup, set the PTAPE5 bit in the
port A pull enable register (PTAPE).
Freescale Semiconductor
Table 3-1. Stop Mode Selection
SPMSC1
1
LVDE LVDSE
x x
1 x
0 Both bits must be 1
0 Either bit a 0
0 Either bit a 0
Chapter 17, "Development
will be near R
IDD
MC9S08QE128 MCU Series Reference Manual, Rev. 2
(SCGC1)."
SPMSC2
PPDC
x Stop modes disabled; illegal opcode reset if STOP
instruction executed
x Stop3 with BDM enabled
x Stop3 with voltage regulator active
0 Stop3
1 Stop2
Support."
levels because internal clocks are enabled.
IDD
NOTE
Chapter 3 Modes of Operation
Stop Mode
2
Table 3-1.
43