ROHS MC9S08QE128 Reference Manual page 64

Chapter 4 Memory
7
R 0
W
Reset: 0
Field
2:0 When the CPU addresses the paging window, 0x8000-0xBFFF, the value in the PPAGE register along with the
XA16:XA14 CPU addresses A13:A0 are used to create a 17-bit extended address.
4.4.2.2 Linear Address Pointer Registers 2:0 (LAP2:LAP0)
The three registers, LAP2:LAP0 contain the 17-bit linear address that allows the user to access any flash
location in the extended address map. This register is used in conjunction with the data registers, linear
byte (LB), linear byte post increment (LBP) and linear word post increment (LWP). The contents of
LAP2:LAP0 will auto-increment when accessing data using the LBP and LWP registers. The contents of
LAP2:LAP0 can be increased by writing an 8-bit value to LAPAB.
7
R 0
W
R
LA15
W
R
LA7
W
Reset: 0
Figure 4-5. Linear Address Pointer Registers 2:0 (LAP2:LAP0)
Table 4-6. Linear Address Pointer Registers 2:0 Field Descriptions
Field
16:0 The values in LAP2:LAP0 are used to create a 17-bit linear address pointer. The value in these registers are used
LA21:LA0 as the extended address when accessing any of the data registers LB, LBP and LWP.
4.4.2.3 Linear Word Post Increment Register (LWP)
This register is one of three data registers that the user can use to access any flash memory location in the
extended address map. When LWP is accessed the contents of LAP2:LAP0 make up the extended address
of the flash memory location to be addressed. When accessing data using LWP, the contents of
LAP2:LAP0 will increment after the read or write is complete.
64
6 5
0 0
0 0
Figure 4-4. Program Page Register (PPAGE)
Table 4-5. Program Page Register Field Descriptions
6 5
0 0
LA14 LA13
LA6 LA5
0 0
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
0 0
XA16
0 0
Description
4 3
0 0
LA12 LA11 LA10
LA4 LA3 LA2
0 0
Description
2 1 0
XA15 XA14
0 1 0
2 1 0
0 0
LA16
LA9 LA8
LA1 LA0
0 0 0
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