Port J Registers - ROHS MC9S08QE128 Reference Manual

Field
7:0 Internal Pull Enable for Port H Bits — Each of these control bits determines if the internal pull-up device is
PTHPE[7:0] enabled for the associated PTH pin. For port H pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port H bit n.
1 Internal pull-up device enabled for port H bit n.
6.5.8.4 Port H Slew Rate Enable Register (PTHSE)
7
R
PTHSE7
W
Reset: 0
Field
7:0 Output Slew Rate Enable for Port H Bits — Each of these control bits determines if the output slew rate control
PTHSE[7:0] is enabled for the associated PTH pin. For port H pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port H bit n.
1 Output slew rate control enabled for port H bit n.
6.5.8.5 Port H Drive Strength Selection Register (PTHDS)
7
R
PTHDS7
W
Reset: 0
Figure 6-48. Drive Strength Selection for Port H Register (PTHDS)
Field
7:0 Output Drive Strength Selection for Port H Bits — Each of these control bits selects between low and high
PTHDS[7:0] output drive for the associated PTH pin. For port H pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port H bit n.
1 High output drive strength selected for port H bit n.
6.5.9

Port J Registers

Port J is controlled by the registers listed below.
Freescale Semiconductor
Table 6-44. PTHPE Register Field Descriptions
6 5
PTHSE6 PTHSE5
0 0
Figure 6-47. Slew Rate Enable for Port H Register (PTHSE)
Table 6-45. PTHSE Register Field Descriptions
6 5
PTHDS6 PTHDS5
0 0
Table 6-46. PTHDS Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
PTHSE4 PTHSE3
0 0
Description
4 3
PTHDS4 PTHDS3
0 0
Description
Chapter 6 Parallel Input/Output Control
2 1
PTHSE2 PTHSE1
0 0
2 1
PTHDS2 PTHDS1
0 0
0
PTHSE0
0
0
PTHDS0
0
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