ROHS MC9S08QE128 Reference Manual page 134

Chapter 6 Parallel Input/Output Control
6.5.8.1 Port H Data Register (PTHD)
7
R
PTHD7
W
Reset: 0
Field
7:0 Port H Data Register Bits — For port H pins that are inputs, reads return the logic level on the pin. For port H
PTHD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port H pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTHD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.
6.5.8.2 Port H Data Direction Register (PTHDD)
7
R
PTHDD7
W
Reset: 0
Field
7:0 Data Direction for Port H Bits — These read/write bits control the direction of port H pins and what is read for
PTHDD[7:0] PTHD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port H bit n and PTHD reads return the contents of PTHDn.
6.5.8.3 Port H Pull Enable Register (PTHPE)
The port H enable register (PTHPE) enables pull-ups on the corresponding PTH pin. In some cases, a
pull-down device will be enabled if pull-downs are supported by an alternative pin function, such as KBI.
7
R
PTHPE7
W
Reset: 0
134
6 5
PTHD6 PTHD5
0 0
Figure 6-44. Port H Data Register (PTHD)
Table 6-42. PTHD Register Field Descriptions
6 5
PTHDD6 PTHDD5
0 0
Figure 6-45. Port H Data Direction Register (PTHDD)
Table 6-43. PTHDD Register Field Descriptions
6 5
PTHPE6 PTHPE5
0 0
Figure 6-46. Internal Pull Enable for Port H Register (PTHPE)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
PTHD4 PTHD3
0 0
Description
4 3
PTHDD4 PTHDD3
0 0
Description
4 3
PTHPE4 PTHPE3
0 0
2 1
PTHD2 PTHD1
0 0
2 1
PTHDD2 PTHDD1
0 0
2 1
PTHPE2 PTHPE1
0 0
Freescale Semiconductor
0
PTHD0
0
0
PTHDD0
0
0
PTHPE0
0