Port Data Set Registers; Port Data Clear Registers; Port Data Toggle Register; Pin Behavior In Stop Modes - ROHS MC9S08QE128 Reference Manual

Chapter 6 Parallel Input/Output Control
6.3.1

Port Data Set Registers

The Port Data Set registers (PTxSET) are write only registers associated with ports C & E. Writing to these
registers has the result: PortData = PortData | SetPattern. A subsequent read of the corresponding port data
register will reflect the changed result (a one clock cycle delay is required to see the proper value).
6.3.2

Port Data Clear Registers

The Port Data Clear registers (PTxCLR) are write only registers associated with ports C & E. Writing to
these registers has the result: PortData = PortData & NOT ClrPattern. A subsequent read of the
corresponding port data register will reflect the changed result (a one clock cycle delay is required to see
the proper value).
6.3.3

Port Data Toggle Register

The Port Data Toggle registers (PTxTOG) are write only registers associated with ports C & E. Writing to
these registers has the result: PortData[i] = NOT PortData[i] for any bit written as a one to PTxTOG. A
subsequent read of the corresponding port data register will reflect the changed result (a one clock cycle
delay is required to see the proper value).
6.4

Pin Behavior in Stop Modes

Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
• Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as
before the STOP instruction was executed. CPU register status and the state of I/O registers should
be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon
recovery from stop2 mode, before accessing any I/O, the user should examine the state of the PPDF
bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had
occurred. If the PPDF bit is 1, I/O register states should be restored from the values saved in RAM
before the STOP instruction was executed and peripherals may require initialization or restoration
to their pre-stop condition. The user must then write a 1 to the PPDACK bit in the SPMSC2
register. Access to I/O is now permitted again in the user application program.
• In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.
6.5

Parallel I/O and Pin Control Registers

This section provides information about the registers associated with the parallel I/O ports. The data and
data direction registers are located in page zero of the memory map. The pull up, slew rate, drive strength,
and interrupt control registers are located in the high page section of the memory map.
Refer to tables in Chapter 4,
pin control registers. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
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"Memory," for the absolute address assignments for all parallel I/O and their
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor