ROHS MC9S08QE128 Reference Manual page 47

Chapter 3 Modes of Operation
Table 3-3. Triggers for Transitions Shown in
Transition #
5
6
7
1
An analog connection from this pin to the on-chip regulator will wake up the regulator, which will then initiate a
power-on-reset sequence.
3.7.1 On-Chip Peripheral Modules in Stop and Low Power Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to
Mode," and Section 3.6.2, "Stop3
When the MCU enters LPWait or LPRun modes, system clocks to the internal peripheral modules continue
based on the settings of the clock gating control registers (SCGC1 and SCGC2).
Peripheral
CPU
RAM
Flash
Port I/O Registers
Port I/O Pins
ADC
ACMPx
BDM
COP
ICS
IICx
IRQ
KBIx
LVD/LVW
RTC
48
From
LPWAIT RUN
RUN LPWAIT
RUN WAIT
WAIT RUN
STOP3 RUN
RUN STOP3
Mode," for specific information on system behavior in stop modes.
Table 3-4. Stop and Low Power Mode Behavior
Stop2
Off
Standby
Off
Off
States Held
Off
Off
3
Off
Off
Off
Off
Wake Up
Off
7
Off
Optionally On
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Figure
To
Interrupt when LPWUI=1
NOT SUPPORTED
WAIT instruction
Interrupt or reset
Interrupt (if LPR = 0, or LPR = 1 and LPWUI =1)
or reset
STOP instruction
Mode
Stop3
Standby
Standby
Standby
Standby
Peripheral Control Peripheral Control
1
Optionally On
2
Optionally On
Optionally On
Off
5
Optionally On
Standby
Optionally On
Optionally On
Optionally On
Optionally On
3-1. (continued)
Trigger
Section 3.6.1, "Stop2
LPWait
Standby
Standby
Standby
Standby
1
Optionally On Optionally On
Optionally On Optionally On
4
Off
Optionally On Optionally On
6
On
Optionally On Optionally On
Optionally On Optionally On
Optionally On Optionally On
8
Off
Optionally On Optionally On
Freescale Semiconductor
LPRun
On
On
On
On
On
1
4
Off
6
On
8
Off