ROHS MC9S08QE128 Reference Manual page 136

Chapter 6 Parallel Input/Output Control
6.5.9.1 Port J Data Register (PTJD)
7
R
PTJD7
W
Reset: 0
Field
7:0 Port J Data Register Bits — For port J pins that are inputs, reads return the logic level on the pin. For port J
PTJD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port J pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTJD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
6.5.9.2 Port J Data Direction Register (PTJDD)
7
R
PTJDD7
W
Reset: 0
Field
7:0 Data Direction for Port J Bits — These read/write bits control the direction of port J pins and what is read for
PTJDD[7:0] PTJD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port J bit n and PTJD reads return the contents of PTJDn.
6.5.9.3 Port J Pull Enable Register (PTJPE)
The port J enable register (PTJPE) enables pull-ups on the corresponding PTJ pin. In some cases, a
pull-down device will be enabled if pull-downs are supported by an alternative pin function, such as KBI.
7
R
PTJPE7
W
Reset: 0
136
6 5
PTJD6 PTJD5
0 0
Figure 6-49. Port J Data Register (PTJD)
Table 6-47. PTJD Register Field Descriptions
6 5
PTJDD6 PTJDD5
0 0
Figure 6-50. Port J Data Direction Register (PTJDD)
Table 6-48. PTJDD Register Field Descriptions
6 5
PTJPE6 PTJPE5
0 0
Figure 6-51. Internal Pull Enable for Port J Register (PTJPE)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
PTJD4 PTJD3
0 0
Description
4 3
PTJDD4 PTJDD3
0 0
Description
4 3
PTJPE4 PTJPE3
0 0
2 1
PTJD2 PTJD1
0 0
2 1
PTJDD2 PTJDD1
0 0
2 1
PTJPE2 PTJPE1
0 0
Freescale Semiconductor
0
PTJD0
0
0
PTJDD0
0
0
PTJPE0
0