Register Descriptions - ROHS MC9S08QE128 Reference Manual

18.3.3

Register Descriptions

This section consists of the DBG register descriptions in address order.
Note: For all registers below, consider: U = Unchanged, bit maintain its value after reset.
18.3.3.1 Debug Comparator A High Register (DBGCAH)
Module Base + 0x0000
7
R
Bit 15
W
POR
or non- 1
end-run
Reset
U
1
end-run
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Field
Bits 15–8 Comparator A High Compare Bits — The Comparator A High compare bits control whether Comparator A will
compare the address bus bits [15:8] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
18.3.3.2 Debug Comparator A Low Register (DBGCAL)
Module Base + 0x0001
7
R
Bit 7
W
POR
or non- 1
end-run
Reset
U
1
end-run
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Freescale Semiconductor
6 5
Bit 14 Bit 13
1 1
U U
Figure 18-2. Debug Comparator A High Register (DBGCAH)
Table 18-3. DBGCAH Field Descriptions
6 5
Bit 6 Bit 5
1 1
U U
Figure 18-3. Debug Comparator A Low Register (DBGCAL)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
Bit 12 Bit 11
1 1
U U
Description
4 3
Bit 4 Bit 3
1 1
U U
Chapter 18 Debug Module (DBG) (128K)
2 1
Bit 10 Bit 9
1 1
U U
2 1
Bit 2 Bit 1
1 1
U U
0
Bit 8
1
U
0
Bit 0
0
U
325