Serial Peripheral Interface (S08Spiv3); Introduction; Spi Clock Gating; Interrupt Vector - ROHS MC9S08QE128 Reference Manual

Chapter 15

Serial Peripheral Interface (S08SPIV3)

15.1

Introduction

Figure 15-1 shows the MC9S08QE128 Series block diagram with the SPI highlighted.
Ignore any references to stop1 low-power mode in this chapter, because the
MC9S08QE128 device does not support it.
15.1.1

SPI Clock Gating

The bus clock to SPI1 and SPI2 can be gated on and off using the SPI1 and SPI2 bits, respectively, in
SCGC2. These bits are set after any reset, which enables the bus clock to this module. To conserve power,
these bits can be cleared to disable the clock to either of these modus when not in use. See
"Peripheral Clock Gating,"
15.1.2

Interrupt Vector

See Section 4.2, "Reset and Interrupt Vector
Freescale Semiconductor
NOTE
for details.
Assignments," for the SPI interrupt vector assignments.
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Section 5.7,
267