Port C Registers - ROHS MC9S08QE128 Reference Manual

Field
7:0 Internal Pull Enable for Port B Bits — Each of these control bits determines if the internal pull-up or pull-down
PTBPE[7:0] device is enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port B bit n.
1 Internal pull-up/pull-down device enabled for port B bit n.
6.5.2.4 Port B Slew Rate Enable Register (PTBSE)
7
R
PTBSE7
W
Reset: 0
Field
7:0 Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control
PTBSE[7:0] is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.
6.5.2.5 Port B Drive Strength Selection Register (PTBDS)
7
R
PTBDS7
W
Reset: 0
Figure 6-12. Drive Strength Selection for Port B Register (PTBDS)
Field
7:0 Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high
PTBDS[7:0] output drive for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port B bit n.
1 High output drive strength selected for port B bit n.
6.5.3

Port C Registers

Port C is controlled by the registers listed below.
Freescale Semiconductor
Table 6-8. PTBPE Register Field Descriptions
6 5
PTBSE6 PTBSE5
0 0
Figure 6-11. Slew Rate Enable for Port B Register (PTBSE)
Table 6-9. PTBSE Register Field Descriptions
6 5
PTBDS6 PTBDS5
0 0
Table 6-10. PTBDS Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
PTBSE4 PTBSE3
0 0
Description
4 3
PTBDS4 PTBDS3
0 0
Description
Chapter 6 Parallel Input/Output Control
2 1
PTBSE2 PTBSE1
0 0
2 1
PTBDS2 PTBDS1
0 0
0
PTBSE0
0
0
PTBDS0
0
119