ROHS MC9S08QE128 Reference Manual page 120

Chapter 6 Parallel Input/Output Control
6.5.3.1 Port C Data Register (PTCD)
7
R
PTCD7
W
Reset: 0
Field
7:0 Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C
PTCD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.
6.5.3.2 Port C Data Direction Register (PTCDD)
7
R
PTCDD7
W
Reset: 0
Field
7:0 Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for
PTCDD[7:0] PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
6.5.3.3 Port C Data Set Register (PTCSET)
7
R
W PTCSET7 PTCSET6
Reset: 0
120
6 5
PTCD6 PTCD5
0 0
Figure 6-13. Port C Data Register (PTCD)
Table 6-11. PTCD Register Field Descriptions
6 5
PTCDD6 PTCDD5
0 0
Figure 6-14. Port C Data Direction Register (PTCDD)
Table 6-12. PTCDD Register Field Descriptions
6 5
PTCSET5
0 0
Figure 6-15. Port C Data Set Register (PTCSET)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
PTCD4 PTCD3
0 0
Description
4 3
PTCDD4 PTCDD3
0 0
Description
4 3
PTCSET4 PTCSET3
0 0
2 1
PTCD2 PTCD1
0 0
2 1
PTCDD2 PTCDD1
0 0
2 1
PTCSET2 PTCSET1
0 0
Freescale Semiconductor
0
PTCD0
0
0
PTCDD0
0
0
PTCSET0
0