ROHS MC9S08QE128 Reference Manual page 198

12-bit Analog-to-Digital Converter (S08ADCV1)
In cases where separate power supplies are used for analog and digital power, the ground connection
between these supplies must be at the V
supplies if possible. The V
10.6.1.2 Analog Reference Pins
In addition to the analog supplies, the ADC module has connections for two reference voltage inputs. The
high reference is V
REFH
reference is V , which may be shared on the same pin as V
REFL
When available on a separate pin, V
driven by an external source that is between the minimum V
must never exceed V
DDAD
voltage potential as V
SSAD
immunity and bypass capacitors placed as near as possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array at each successive
approximation step is drawn through the V
current demand is a 0.1 μF capacitor with good high frequency characteristics. This capacitor is connected
between V and V
REFH
path is not recommended because the current will cause a voltage drop which could result in conversion
errors. Inductance in this path must be minimum (parasitic only).
10.6.1.3 Analog Input Pins
The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control
is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be
performed on inputs without the associated pin control register bit set. It is recommended that the pin
control register bit always be set when using a pin as an analog input. This avoids problems with contention
because the output buffer will be in its high impedance state and the pullup is disabled. Also, the input
buffer draws DC current when its input is not at either V
all pins used as analog inputs should be done to achieve lowest operating current.
Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise
or when the source impedance is high. Use of 0.01 μF capacitors with good high-frequency characteristics
is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as
possible to the package pins and be referenced to V
For proper conversion, the input voltage must fall between V
exceeds V , the converter circuit converts the signal to $FFF (full scale 12-bit representation), $3FF
REFH
(full scale 10-bit representation) or $FF (full scale 8-bit representation). If the input is equal to or less than
V , the converter circuit converts it to $000. Input voltages between V
REFL
linear conversions. There will be a brief current associated with V
charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles
when ADLSMP is high.
For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be
transitioning during conversions.
198
pin. This should be the only ground connection between these
SSAD
pin makes a good single point ground location.
SSAD
, which may be shared on the same pin as V
may be connected to the same potential as V
REFH
). When available on a separate pin, V
. Both V and V
REFH
REFH
and must be placed as near as possible to the package pins. Resistance in the
REFL
MC9S08QE128 MCU Series Reference Manual, Rev. 2
DDAD
on some devices.
SSAD
spec and the V
DDAD
REFL
must be routed carefully for maximum noise
REFL
and V loop. The best external component to meet this
REFL
or V . Setting the pin control register bits for
DD SS
.
SSA
and V
REFH
REFL
on some devices. The low
, or may be
DDAD
potential (V
DDAD
must be connected to the same
. If the input is equal to or
REFL
and V are straight-line
REFH REFL
when the sampling capacitor is
Freescale Semiconductor
REFH