System Power Management Status And Control 1 Register (Spmsc1) - ROHS MC9S08QE128 Reference Manual

Chapter 5 Resets, Interrupts, and General System Control
Field
7:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
ID[7:0] MC9S08QE128 is hard coded to the value 0x015. See also ID bits in
5.8.7 System Power Management Status and Control 1 Register
(SPMSC1)
This high page register contains status and control bits to support the low voltage detect function, and to
enable the bandgap voltage reference for use by the ADC module. To configure the low voltage detect trip
voltage, see Table 5-12
7
R LVDF
W
Reset: 0
Stop2
u
Wakeup:
= Unimplemented or Reserved
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
1
Bit 1 is a reserved bit that must always be written to 0.
2
This bit can be written only one time after reset. Additional writes are ignored.
Field
7 Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
LVDF
6 Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
LVDACK (write 1 to clear LVDF). Reads always return 0.
5 Low-Voltage Detect Interrupt Enable — This bit enables hardware interrupt requests for LVDF.
LVDIE 0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
4 Low-Voltage Detect Reset Enable — This write-once bit enables LVDF events to generate a hardware reset
LVDRE (provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
3 Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
LVDSE detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
104
Table 5-9. SDIDL Register Field Descriptions
for the LVDV bit description in SPMSC3.
6 5
0
LVDIE
LVDACK
0 0
0 u
Table 5-10. SPMSC1 Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
2
LVDRE LVDSE
1 1
u u
Description
Table 5-8.
1
2 1
0
2
LVDE
1 0
u 0
u = Unaffected by reset
Freescale Semiconductor
0
BGBE
0
u