ROHS MC9S08QE128 Reference Manual page 130

Chapter 6 Parallel Input/Output Control
6.5.6.1 Port F Data Register (PTFD)
7
R
PTFD7
W
Reset: 0
Field
7:0 Port F Data Register Bits — For port F pins that are inputs, reads return the logic level on the pin. For port F
PTFD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
6.5.6.2 Port F Data Direction Register (PTFDD)
7
R
PTFDD7
W
Reset: 0
Field
7:0 Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for
PTFDD[7:0] PTFD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.
6.5.6.3 Port F Pull Enable Register (PTFPE)
The port F enable register (PTFPE) enables pull-ups on the corresponding PTF pin. In some cases, a
pull-down device will be enabled if pull-downs are supported by an alternative pin function, such as KBI.
7
R
PTFPE7
W
Reset: 0
130
6 5
PTFD6 PTFD5
0 0
Figure 6-34. Port F Data Register (PTFD)
Table 6-32. PTFD Register Field Descriptions
6 5
PTFDD6 PTFDD5
0 0
Figure 6-35. Port F Data Direction Register (PTFDD)
Table 6-33. PTFDD Register Field Descriptions
6 5
PTFPE6 PTFPE5
0 0
Figure 6-36. Internal Pull Enable for Port F Register (PTFPE)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
PTFD4 PTFD3
0 0
Description
4 3
PTFDD4 PTFDD3
0 0
Description
4 3
PTFPE4 PTFPE3
0 0
2 1
PTFD2 PTFD1
0 0
2 1
PTFDD2 PTFDD1
0 0
2 1
PTFPE2 PTFPE1
0 0
Freescale Semiconductor
0
PTFD0
0
0
PTFDD0
0
0
PTFPE0
0