ROHS MC9S08QE128 Reference Manual page 328

Chapter 18 Debug Module (DBG) (128K)
18.3.3.6 Debug Comparator C Low Register (DBGCCL)
Module Base + 0x0005
7
R
Bit 7
W
POR
or non- 0
end-run
Reset
U
1
end-run
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Field
Bits 7–0 Comparator C Low Compare Bits — The Comparator C Low compare bits control whether Comparator C will
compare the address bus bits [7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
18.3.3.7 Debug FIFO High Register (DBGFH)
Module Base + 0x0006
7
R Bit 15
W
POR
or non- 0
end-run
Reset
U
1
end-run
= Unimplemented or Reserved
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
328
6 5
Bit 6 Bit 5
0 0
U U
Figure 18-7. Debug Comparator C Low Register (DBGCCL)
Table 18-8. DBGCCL Field Descriptions
6 5
Bit 14 Bit 13
0 0
U U
Figure 18-8. Debug FIFO High Register (DBGFH)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
Bit 4 Bit 3
0 0
U U
Description
4 3
Bit 12 Bit 11
0 0
U U
2 1
Bit 2 Bit 1
0 0
U U
2 1
Bit 10 Bit 9
0 0
U U
Freescale Semiconductor
0
Bit 0
0
U
0
Bit 8
0
U