ROHS MC9S08QE128 Reference Manual page 68

Chapter 4 Memory
4.4.3.1.3 Data Space
The linear address pointer registers, LAP2:LAP0 along with the linear data register allow the CPU to read
or write any address in the extended flash memory space. This linear address pointer may be used to access
data from any memory location while executing code from any location in extended memory, including
accessing data from a different PPAGE than the currently executing program.
To access data using the linear address pointer, the user would first setup the extended address in the 22-bit
address pointer, LAP2:LAP0. Accessing one of the three linear data registers LB, LBP and LWP will
access the extended memory location specified by LAP2:LAP0. The three linear data registers access the
memory locations in the same way, however the LBP and LWP will also increment LAP2:LAP0.
Accessing either the LBP or LWP registers allows a user program to read successive memory locations
without re-writing the linear address pointer. Accessing LBP or LWP does the exact same function.
However, because of the address mapping of the registers with LBP following LWP, a user can do word
accesses in the extended address space using the LDHX or STHX instructions to access location LWP.
The MMU supports the addition of a 2s compliment value to the linear address pointer without using any
math instructions or memory resources. Writes to LAPAB with a 2s compliment value will cause the
MMU to add that value to the existing value in LAP2:LAP0.
4.4.3.1.4 PPAGE and Linear Address Pointer to Extended Address
See Figure 4-1, on how the program PPAGE memory pages and the Linear Address Pointer are mapped to
extended address space.
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MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor