ROHS MC9S08QE128 Reference Manual page 137

Field
7:0 Internal Pull Enable for Port J Bits — Each of these control bits determines if the internal pull-up device is
PTJPE[7:0] enabled for the associated PTJ pin. For port J pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port J bit n.
1 Internal pull-up device enabled for port J bit n.
6.5.9.4 Port J Slew Rate Enable Register (PTJSE)
7
R
PTJSE7
W
Reset: 0
Field
7:0 Output Slew Rate Enable for Port J Bits — Each of these control bits determines if the output slew rate control
PTJSE[7:0] is enabled for the associated PTJ pin. For port J pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port J bit n.
1 Output slew rate control enabled for port J bit n.
6.5.9.5 Port J Drive Strength Selection Register (PTJDS)
7
R
PTJDS7
W
Reset: 0
Figure 6-53. Drive Strength Selection for Port J Register (PTJDS)
Field
7:0 Output Drive Strength Selection for Port J Bits — Each of these control bits selects between low and high
PTJDS[7:0] output drive for the associated PTJ pin. For port J pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port J bit n.
1 High output drive strength selected for port J bit n.
Freescale Semiconductor
Table 6-49. PTJPE Register Field Descriptions
6 5
PTJSE6 PTJSE5
0 0
Figure 6-52. Slew Rate Enable for Port J Register (PTJSE)
Table 6-50. PTJSE Register Field Descriptions
6 5
PTJDS6 PTJDS5
0 0
Table 6-51. PTJDS Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
PTJSE4 PTJSE3
0 0
Description
4 3
PTJDS4 PTJDS3
0 0
Description
Chapter 6 Parallel Input/Output Control
2 1
PTJSE2 PTJSE1
0 0
2 1
PTJDS2 PTJDS1
0 0
0
PTJSE0
0
0
PTJDS0
0
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