ROHS MC9S08QE128 Reference Manual page 336

Chapter 18 Debug Module (DBG) (128K)
The DBG trigger register (DBGT) can not be changed unless ARM=0.
18.3.3.15 Debug Status Register (DBGS)
Module Base + 0x000E
7
R AF
W
POR
or non- 0
end-run
Reset
U
1
end-run
= Unimplemented or Reserved
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, ARMF gets cleared by reset but AF, BF, and CF do not
change after reset.
Field
7 Trigger A Match Bit — The AF bit indicates if Trigger A match condition was met since arming.
AF 0 Comparator A did not match
1 Comparator A match
6 Trigger B Match Bit — The BF bit indicates if Trigger B match condition was met since arming.
BF 0 Comparator B did not match
1 Comparator B match
5 Trigger C Match Bit — The CF bit indicates if Trigger C match condition was met since arming.
CF 0 Comparator C did not match
1 Comparator C match
0 Arm Flag Bit — The ARMF bit indicates whether the debugger is waiting for trigger or waiting for the FIFO to fill.
ARMF While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. See
the DBG Module"
0 Debugger not armed
1 Debugger armed
336
Table 18-17. Trigger Mode Encoding
TRG Value
1001
↓
1111
6 5
BF CF
0 0
U U
Figure 18-16. Debug Status Register (DBGS)
Table 18-18. DBGS Field Descriptions
for more information.
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Meaning
No Trigger
NOTE
4 3
0 0
0 0
0 0
Description
2 1
0 0 ARMF
0 0
0 0
Section 18.4.4.2, "Arming
Freescale Semiconductor
0
1
0