ROHS MC9S08QE128 Reference Manual page 128

Chapter 6 Parallel Input/Output Control
7
R
PTEPE7
W
Reset: 0
Field
7:0 Internal Pull Enable for Port E Bits — Each of these control bits determines if the internal pull-up device is
PTEPE[7:0] enabled for the associated PTE pin. For port E pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port E bit n.
1 Internal pull-up device enabled for port E bit n.
6.5.5.7 Port E Slew Rate Enable Register (PTESE)
7
R
PTESE7
W
Reset: 0
Field
7:0 Output Slew Rate Enable for Port E Bits — Each of these control bits determines if the output slew rate control
PTESE[7:0] is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.
128
6 5
PTEPE6 PTEPE5
0 0
Figure 6-31. Internal Pull Enable for Port E Register (PTEPE)
Table 6-29. PTEPE Register Field Descriptions
6 5
PTESE6 PTESE5
0 0
Figure 6-32. Slew Rate Enable for Port E Register (PTESE)
Table 6-30. PTESE Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
PTEPE4 PTEPE3
0 0
Description
4 3
PTESE4 PTESE3
0 0
Description
2 1
PTEPE2 PTEPE1
0 0
2 1
PTESE2 PTESE1
0 0
Freescale Semiconductor
0
PTEPE0
0
0
PTESE0
0