Modes Of Operation; Block Diagram; Signal Description - ROHS MC9S08QE128 Reference Manual

Chapter 18 Debug Module (DBG) (128K)
• Ability to End-trace until reset and Begin-trace from reset
18.1.2

Modes of Operation

The on-chip ICE system can be enabled in all MCU functional modes. The DBG module is disabled if the
MCU is secure. The DBG module comparators are disabled when executing a Background Debug Mode
(BDM) command.
18.1.3

Block Diagram

Figure 18-1 shows the structure of the DBG module.
core_cpu_aob_14_t2
core_cpu_aob_15_t2
core_ppage_t2[2:0]
DBG Read Data Bus
Address Bus[16:0]
Write Data Bus
Read Data Bus
Read/Write
DBG Module Enable
mmu_ppage_sel
core_cof[1:0]
MCU in BDM
MCU reset
Instr. Lastcycle
register
Bus Clk
subtract 2
Write Data Bus
Read Data Bus
Read/Write
1. In 64K versions of this module there are only 16 address lines [15:0], there are no core_cpu_aob_14_t2,
core_cpu_aob_15_t2, core_ppage_t2[2:0], and ppage_sel signals.
18.2

Signal Description

The DBG module contains no external signals.
322
1
1
1
1
Address/Data/Control Registers
c
o
n
t
r
Comparator A
o
l
Comparator B
1
Comparator C
Change of Flow Indicators
m
u
x
m
u
x
Figure 18-1. DBG Block Diagram
MC9S08QE128 MCU Series Reference Manual, Rev. 2
FIFO Data
control
match_A
match_C
event only
ppage_sel
8 deep
m
FIFO
u
addr[16:0]
x
Trigger
Break
Control
match_B
Logic
store
1
m
FIFO Data
u
x
1
Freescale Semiconductor
Tag
Force
Read DBGFL
Read DBGFH
Read DBGFX