ROHS MC9S08QE128 Reference Manual page 329

Field
Bits 15–8 FIFO High Data Bits — The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register
is not used in event only modes and will read a $00 for valid FIFO words.
18.3.3.8 Debug FIFO Low Register (DBGFL)
Module Base + 0x0007
7
R Bit 7
W
POR
or non- 0
end-run
Reset
U
1
end-run
= Unimplemented or Reserved
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Field
Bits 7–0 FIFO Low Data Bits — The FIFO Low data bits contain the least significant byte of data in the FIFO. When
reading FIFO words, read DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the
FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX
and DBGFH so it is not necessary to read them before reading DBGFL.
Freescale Semiconductor
Table 18-9. DBGFH Field Descriptions
6 5
Bit 6 Bit 5
0 0
U U
Figure 18-9. Debug FIFO Low Register (DBGFL)
Table 18-10. DBGFL Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
Bit 4 Bit 3
0 0
U U
Description
Chapter 18 Debug Module (DBG) (128K)
2 1
Bit 2 Bit 1
0 0
U U
0
Bit 0
0
U
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